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Timing influenced general-cell genetic floorplanner. MICROELECTRONICS JOURNAL 28 (2): 151-166 FEB 1997.

CMOS/BiCMOS mixed design using tabu search. ELECTRONICS LETTERS 34 (14): 1395-1396 JUL 9 1998.

A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999.

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(2006) A Parallel Algorithm for Inverse Halftoning and its Hardware. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.

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Conference or Workshop Item

(2007) Effective Parallelization of Stochastic Evolution. In: ISDA'07 Conference. (Unpublished)

(2006) Parallel Stochastic Evolution Algorithms for Constrained Multiobjective Optimization. In: SNPD'07. (Unpublished)

Trends in Internet Usage & its Social Effects in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

“Summary Report” Structure of National IT Plan for Saudi Arabia. In: Department of Computer Engineering, KFUPM.

Tabu Search Based Circuit Optimization. In: Department of Computer Engineering, KFUPM.

(2005) Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm. In: International Symposium on Circuits and Systems, (ISCAS 05), Kobe, Japan.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: International Symposium on Circuits and Systems, (ISCAS 06), Kos, Greece.

Strategy Planning for Higher Education Project Horizon. In: King Fahd University of Petroleum & Minerals.

The Aafaq Web. In: Department of Computer Engineering, KFUPM.

(2001) Iterative Heuristics for Timing & low power VLSI standard cell placement. In: Unknown. (Unpublished)

Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

The COE Department. In: Computer Engineering Department, KFUPM.

Transmission Media. In: Department of Computer Engineering, KFUPM.

Use and Effect of Internet in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

WWW & E-Commerce. In: Department of Computer Engineering, KFUPM.

(2006) Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. In: International Parallel and Distributed Processing Symposium, April, 2006, Rhodes Island, Greece.

(2005) Comparative Evaluation of Parallelization Strategies for Evolutionary and Stochastic Heuristics. In: Genetic and Evolutionary Computation Conference (GECCO-2005),, 25-29 June, 2005, Washington D.C. , USA.

(2005) Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning. In: Unknown.

FUZZIFIED SIMULATED EVOLUTION ALGORITHM FOR MULTI-OBJECTIVE OPTIMIZATION OF COMBINATIONAL LOGIC CIRCUITS. In: Computer Engineering Department, KFUPM.

Fast Fuzzy Force-Directed/Simulated Evolution Metaheuristic for Multiobjective VLSI Cell Placement. In: Department of Computer Engineering, KFUPM.

(2001) Modern Iterative Algorithms and thier Applications in Computer Engineering. In: Book.

EFFICIENT COMBINATIONAL CIRCUITS DESIGN THROUGH FUZZIFIED ANT COLONY OPTIMIZATION ALGORITHM. In: Computer Engineering Department, KFUPM.

Computer Engineering Department Research Profile. In: Computer Engineering Department, KFUPM.

Information Technology Center (ITC) Services and Projects. In: Supporting excellence via technology, KFUPM.

CCSE PAST & PRESENT STANDING. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

(2003) Iterative Computer Algorithms with Applications in Engineering-Chapter 2: Partitioning. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

Chapter 1: Introduction to VLSI Physical Design. In: King Fahd University of Petroleum & Minerals.

Automating Your Schedule. In: Special Mini Talk/Demo for 993 Summer, Dhahran, Saudi Arabia.

An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation. In: An Iterative Heuristic for State Justification in, Dhahran, Saudi Arabia.

Area-Time Optimal Adder with Relative Placement Generator. In: Area-Time Optimal Adder with Relative Placement Generator.

Iterative Computer Algorithms: and their applications in engineering. In: Special Talk for Motorola CAD Group,.

(2000) A Parallel Tabu Search Algorithm for VLSI Standard-Cell Placement. In: IEEE International Symposium on Circuits and Systems'', Geneva.

(2000) Fuzzy Simulated Evolution Algorithm for Topology Design on Campus Networks. In: IEEE Congress on Evolutionary Computation, San Diego, USA.

(1999) Fuzzy Simulated Evolution Algorithm for Multiobjective Optimization of VLSI Placement. In: IEEE Congress on Evolutionary Computation, Washington DC.

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(1995) Timing Driven Genetic Algorithm for Placement. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1995) Performance Driven Standard-cell Placement Using the Genetic Algorithm. In: Fifth Great Lakes Symposium on VLSI, GLSVLSI'95, Buffalo, USA.

(1995) Loop based scheduling for high level synthesis. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

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(1994) ASIC Design with AHPL. In: IEEE Melecon'94.

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(1992) VLSI Implementation of Controllers for Communication Protocols from their Petri Net Models. In: IEEE International Symposium on Circuits and Systems, California.

(1991) A State Machine Synthesizer with Weinberger Arrays. In: The IEEE Pacific RIM Conference, Victoria, Canada.

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(1994) GSA: Scheduling and Allocation using Genetic Algorithm. In: European Design Automation Conference with Euro-VHDL, Euro-DAC'94, Grenoble.

(1998) Tabu Search Based Circuit Optimization. In: Great Lakes Symposium on VLSI, GLSVLSI'98, SW Louisiana.

(1998) Performance and Interface Buffer Size Driven Behavioral Partitioning for Embedded Systems. In: 9th International Workshop on Rapid Systems Prototyping, IEEE Computer Society Sponsored, Leuven, Belgium.

(1998) Buffer Size Driven Partitioning for HW/SW Co-Design. In: IEEE International Conference on Computer Design, ICCD'98, Austin, USA.

(1999) A High-Performance Hardware-EÆcient Memory Allocation Technique and Design. In: IEEE International Conference on Computer Design, ICCD'99, Austin, USA.

(2001) Task Matching and Scheduling in Heterogeneous Systems Using Simulated Evolution. In: 10th Heterogeneous Computing Workshop in conjunction with IPDPS 2001, San Francisco.

(2001) Fuzzy Evolutionary Hybrid Metaheuristic for Network Topology Design. In: International Conference on Evolutionary Multi-Criterion Optimization, EMO'01, ETH Zurich, Switzerland (A Springer Publication).

(2001) Adaptive Bias Simulated Evolution Algorithm for Placement. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) A Fast Constructive Algorithm For Fixed Channel Assignment Problem. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) Fuzzy Evolutionary Algorithm for VLSI Placement, (Spector, L., E. Goodman, A. Wu, W. B. Langdon, H.-M. Voigt, M. Gen, S. Sen, M. Dorigo, S. Pezeshk, M. Garzon, and E. Burke, editors). In: Proceedings of the Genetic and Evolutionary Computation Conference, GECCO-2001, San Francisco, CA.

(2001) An Evolutionary Algorithm for Network Topology Design. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzy Simulated Evolution for Power and Performance Optimization of VLSI Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Iterative Heuristics for Multiobjective VLSI Cell Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. In: IEEE International Conference on Computer Design, ICCD'2001, Austin.

(2002) HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) PERFORMANCE AND LOW POWER DRIVEN VLSI STANDARD CELL PLACEMENT USING TABU SEARCH. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) FUZZY AGGREGATING FUNCTIONS FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE International Conference on Fuzzy Systems', Honolulu, Hawaii, USA.

(2002) FUZZY BIASLESS SIMULATED EVOLUTION FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2003) Parallel Tabu Search in a Heterogeneous Environment. In: Proceedings of 17th International Parallel & Distributed Processing Symposium.

(2003) GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Simulated Evolution Algorithm For Multiobjective VLSI Netlist Bi-Partitioning. In: IEEE International Symposium on Circuits and Systems', Bangkok, Thailand.

(2003) AREA-TIME OPTIMAL ADDER WITH RELATIVE PLACEMENT GENERATOR. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part I: Enumerative Techniques. In: IEEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part II: Iterative Techniques. In: EEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING. In: IEEE International Symposium on Circuits and Systems, Sharjah, UAE.

(2003) Digital Circuit Design Through Simulated Evolution (SimE). In: IEEE Congress on Evolutionary Computation (CEC),, Canberra, Australia.

(2003) A Modified Ant Colony Algorithm for Evolutionary Design of Digital Circuits. In: IEEE Congress on Evolutionary Computation, Canberra, Australia.

(2003) Ant Colony Algorithm for Evolutionary Design of Arithmetic Circuits. In: Proceedings of the 15th International Conference, Cairo, Egypt.

(2004) FAST FORCE-DIRECTED/SIMULATED EVOLUTION HYBRID FOR MULTIOBJECTIVE VLSI CELL PLACEMENT. In: IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada.

(2004) Fuzzified Ant Colony Optimization Algorithm for Efficient Combinational Circuits Synthesis. In: IEEE Congress on Evolutionary Computation (CEC),, Portland Oregon, USA.

(2004) Enhanced Simulated Evolution Algorithm For Digital Circuit Design Yielding Faster Execution in a Larger Solution Space. In: IEEE Congress on Evolutionary Computation (CEC),, Portland, Oregon, USA.

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. In: International Symposium on Circuits and Systems, (ISCAS 05),, Kobe, Japan.

(2005) Multiobjective VLSI Cell Placement using Distributed Genetic Algorithm. In: Genetic and Evolutionary Computation Conference (GECCO-2005), Washington D.C. , USA.

(2005) Efficient Static Compaction Techniques for Sequential Circuits based on Reverse Order Restoration Based and Test Relaxation. In: Proceedings of the 14th Asian Test Symposium (ATS ’05), Kolkata, India.

(2006) An Enhanced Estimator to Multi-objective OSPF WeightSetting Problem. In: Proceedings of 2006 IEEE/IFIP Network Operations & Management Symposium (NOMS 2006),, Vancouver, Canada.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: Proceedings of 2006 International Symposium in Circuits and Systems, pages 4615-4618, (ISCAS 2006), Island of Kos, Greece.

(2006) Finite State Machine State Assignment for Area and Power Minimization. In: Proceedings of 2006 International Symposium in Circuits and Systems, (ISCAS 2006), Island of Kos, Greece.

(2006) A Heuristics Based Approach for Cellular Mobile Network Planning. In: The International Wireless Communications and Mobile Computing Conference (IWCMC06), Vancouver, Canada.

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. In: IEEE Symposium on Circuits and Systems (ISCAS) 2005, Kobe, Japan.