In this section

    VLSI LAYOUT GENERATION OF A PROGRAMMABLE CRC CHIP

    VLSI LAYOUT GENERATION OF A PROGRAMMABLE CRC CHIP. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 39 (4): 911-916 NOV 1993.

    [img]
    Preview
    		 PDF
    J_Sait_CE_November1993.pdf
    Download (694kB) | Preview

    Abstract

    VLSI layout generation of a programable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. the second stage of the compilation process generates a netlist of logic gates. The netlist so produced is translated to RNL compatible netlist by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout sub-system of VPNR is used to generate the VLSI layout of the programmable CRC chip from the RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in MAGIC layout editor and simulated by irsim at transistor level. The CRC chip can be used in a number applications. These include areas such as data communication for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfers.

    Item Type: Article
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: AbdulRahman
    Date Deposited: 11 Mar 2008 06:25
    Last Modified: 01 Nov 2019 13:23
    URI: http://eprints.kfupm.edu.sa/id/eprint/296