A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder

(1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1.

[img]
Preview
PDF
14067_1.pdf

Download (18kB) | Preview
[img] Microsoft Word
14067_2.doc

Download (26kB)

Abstract

A novel systolic architecture for Viterbi decoding is presented. It consists of two blocks of processors. The first contains a column of processors which perform branch metric computation and decide on the survived branches. The second consists of a matrix of simpler processors which update survived paths and provide the decoded output. The systolic algorithm is modeled in AHPL to verify functional correctness. Implementation details are discussed. It is found that the proposed systolic design compares favorably with previous implementations of Viterbi decoders in terms of speed and modularity

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 13:21
Last Modified: 01 Nov 2019 14:04
URI: https://eprints.kfupm.edu.sa/id/eprint/14067