The architecture of a highly reconfigurable RISC dataflow array processor

The architecture of a highly reconfigurable RISC dataflow array processor. INTERNATIONAL JOURNAL OF ELECTRONICS 83 (4): 493-518 OCT 1997.


Download (3MB) | Preview


The architectural design and VLSi implementation of a highly reconfigurable dataflow RISC processing element (PE) are presented. This processor forms an element of a processor array which possess the features of both static and dynamic dataflow models. The array can be programmed to execute arbitrary algorithms in both static and dynamic manner. The processor array is modelled at the behavioural level in VHDl. The gate level implementation and VLSi layout of both the PE and the array are obtained with the help of OASIS silicon compiler by translating the functionality. The design is validated at all levels of abstraction. The results of simulation of the PE array are presented. The architecture is compared with previous approaches. The prototype PE requires 4261 CMOS gates and uses an are of 7512*8081 micro meter squared

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AbdulRahman
Date Deposited: 15 Mar 2008 07:17
Last Modified: 01 Nov 2019 13:23