Design of a programmable length FIFO memory and its controller.

(1988) Design of a programmable length FIFO memory and its controller. International Journal of Electronics, 65 (5). pp. 923-932.

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Abstract

This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.

Item Type: Article
Subjects: Electrical
Department: College of Engineering and Physics > Electrical Engineering
Depositing User: ANKAR (g200603940) (g200603940)
Date Deposited: 12 May 2008 08:00
Last Modified: 01 Nov 2019 13:26
URI: https://eprints.kfupm.edu.sa/id/eprint/1267