Performance driven standard-cell placement using the geneticalgorithm

(1995) Performance driven standard-cell placement using the geneticalgorithm. VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on, 1.

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Abstract

Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of -criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 13:51
Last Modified: 01 Nov 2019 14:07
URI: https://eprints.kfupm.edu.sa/id/eprint/14832