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    Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement

    Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

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    KFUPM.COE.Iterate.221.Progress.Report2.Mar.2002.pdf
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    Item Type: Conference or Workshop Item (Other)
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: AbdulRahman
    Date Deposited: 08 Mar 2008 05:14
    Last Modified: 01 Nov 2019 13:22
    URI: http://eprints.kfupm.edu.sa/id/eprint/201