A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation

A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.

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Abstract

Abstract Lookup Table (LUT) method for inverse halftoning is computation less, fast and also yields goods results. This paper proposes a parallel algorithm for inverse halftoning by parallelizing the LUT method of inverse halftoning. The LUT method for inverse halftoning is parallelized by dividing the single Look-Up Table of LUT method for inverse halftoning into many smaller Look-up Tables (sLUTs). In the parallel algorithm up-to four pixels can be fetched from the halftone image concurrently and go to their separate smaller Look-Up Tables (sLUT) from where each template fetches its inverse halftone value independent to other pixels. The parallelization can increase the speed of inverse halftoning by up-to 4 times while the total entries in all smaller Look-Up Tables (sLUTs) remains equal to the entries in the single LUT of LUT method for inverse halftoning. Some degradation in image quality is noticed due to parallelization. The complete implementation of the method takes two CPLD devices with external content addressable memories (CAM) and static RAMs to store sLUTs. Keywords: (1) Inverse Halftoning (2) Hardware Implementation (3) Look-Up Table Inverse Halftoning (4) Complex Programmable Logic Devices (CPLD) (5) Image Processing

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AbdulRahman
Date Deposited: 09 Mar 2008 11:11
Last Modified: 01 Nov 2019 13:23
URI: https://eprints.kfupm.edu.sa/id/eprint/254