VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES

VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995.

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Abstract

A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue. Keywords: VLSI design; systolic tree architecture; automated layout

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AbdulRahman
Date Deposited: 11 Mar 2008 04:53
Last Modified: 01 Nov 2019 13:23
URI: https://eprints.kfupm.edu.sa/id/eprint/292