(2008) Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning. Arabian Journal of Science and Engineering (AJSE).

(2000) Fuzzy simulated evolution algorithm for topology design of campusnetworks. Evolutionary Computation, 2000. Proceedings of the 2000 Congress on, 1.

(1995) Performance driven standard-cell placement using the geneticalgorithm. VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on, 1.

(2003) Parallel tabu search in a heterogeneous environment. Parallel and Distributed Processing Symposium, 2003. Proceedings. International, 1.

Timing influenced general-cell genetic floorplanner. Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International conference Hardware Description Languages, 1.

(1992) High level synthesis of controllers for communication protocols. Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on, 4.

(1995) Designing ASICs with UAHPL. Circuits and Devices Magazine, IEEE, 11.

(2004) Enhanced simulated evolution algorithm for digital circuit design yielding faster execution in a larger solution space. Evolutionary Computation, 2004. CEC2004. Congress on, 2.

(2006) Evaluating parallel simulated evolution strategies for VLSI cell placement. Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, 1.

(2001) Adaptive bias simulated evolution algorithm for placement. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 5.

(1999) Fuzzy simulated evolution algorithm for multi-objectiveoptimization of VLSI placement. Evolutionary Computation, 1999. CEC 99. Proceedings of the 1999 Congress on, 1.

(1995) Hardware design and VLSI implementation of a byte-wise CRCgenerator chip. Consumer Electronics, IEEE Transactions on, 41.

(2004) Fast force-directed/simulated evolution hybrid for multiobjective VLSI cell placement. Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, 5.

(1998) Tabu search based circuit optimization. VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on, 1.

(2002) HPTS: heterogeneous parallel tabu search for VLSI placement. Evolutionary Computation, 2002. CEC '02. Proceedings of the 2002 Congress on, 1.

(2002) Fuzzy aggregating functions for multiobjective VLSI placement. Fuzzy Systems, 2002. FUZZ-IEEE'02. Proceedings of the 2002 IEEE International conference, 2.

(2006) Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 1.

(1995) Timing influenced force directed floorplanning. Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European, 1.

(2001) Iterative heuristics for multiobjective VLSI standard cellplacement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 3.

(1995) Timing driven genetic algorithm for standard-cell placement. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

(2003) Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

(1995) Loop based scheduling for high level synthesis. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

(1999) A high-performance hardware-efficient memory allocation techniqueand design. Computer Design, 1999. (ICCD '99) International conference, 1.

(2001) Fuzzified iterative algorithms for performance driven low powerVLSI placement. Computer Design, 2001. ICCD 2001. Proceedings. 2001 International conference, 1.

(2001) An evolutionary meta-heuristic for state justification insequential automatic test pattern generation. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(2003) A modified ant colony algorithm for evolutionary design of digital circuits. Evolutionary Computation, 2003. CEC '03. The 2003 Congress on, 1.

(2003) Reliability and fault tolerance based topological optimization of computer networks - part I: enumerative techniques. Communications, Computers and signal Processing, 2003. PACRIM. 2003 IEEE Pacific Rim conference, 2.

(2003) General iterative heuristics for VLSI multiobjective partitioning. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

(2006) Finite state machine state assignment for area and power minimization. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 1.

(2003) Reliability and fault tolerance based topological optimization of computer networks - part II: iterative techniques. Communications, Computers and signal Processing, 2003. PACRIM. 2003 IEEE Pacific Rim conference, 2.

(1994) ASIC design with AHPL. Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean, 1.

(2006) SimE/TS fuzzy hybrid for multiobjective VLSI placement. Electronics Letters, 42.

(1993) VLSI layout generation of a programmable CRC chip. Consumer Electronics, IEEE Transactions on, 39.

(2003) Digital circuit design through simulated evolution (SimE). Evolutionary Computation, 2003. CEC '03. The 2003 Congress on, 1.

(2001) Fuzzy simulated evolution for power and performance optimization ofVLSI placement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(1995) A novel technique for fast multiplication. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

(2002) Performance and low power driven VLSI standard cell placement usingtabu search. Evolutionary Computation, 2002. CEC '02. Proceedings of the 2002 Congress on, 1.

(2001) A fast constructive algorithm for fixed channel assignment problem. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 5.

(1992) Integrating UAHPL-DA systems with VLSI design tools to support VLSIDA courses. Education, IEEE Transactions on, 35.

(2001) An evolutionary algorithm for network topology design. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(2004) Fuzzified ant colony optimization algorithm for efficient combinational circuits synthesis. Evolutionary Computation, 2004. CEC2004. Congress on, 2.

(1998) CMOS/BiCMOS mixed design using tabu search. Electronics Letters, 34.

(1989) A systolic algorithm for VLSI design of a 1/N rate Viterbi decoder. Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean, 1.

(1992) VLSI implementation of controllers for communication protocols fromtheir Petri net models. VLSI, 1992., Proceedings of the Second Great Lakes Symposium on, 1.

(2005) Parallel algorithm for hardware implementation of inverse halftoning. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 1.

A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design. IEEEGCC 2007.

Reliability based Topological Optimization of Computer Networks - Part II: Iterative Techniques. IEEETEM2003.

GATS: A Novel Hybrid Algorithm for Multiobjective Cell Placement in VLSI Circuit Design. IEEETEM2003.

A METHODOLOGY FOR NETWORK TOPOLOGY DESIGN USING FUZZY EVALUATIONS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

EVOLUTIONARY HEURISTICS FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

(1988) Design of a programmable length FIFO memory and its controller. International Journal of Electronics, 65 (5). pp. 923-932.

(1987) Research note. A CMOS cell for parallelly loadable counters. International Journal of Electronics,, 63 (6). pp. 867-871.

Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. Evaluating Parallel Simulated Evolution Strategies for VLSI Cell.

EFFICIENT ALGORITHM FOR WEINBERGER ARRAY FOLDING. INTERNATIONAL JOURNAL OF ELECTRONICS 69 (4): 509-518 OCT 1990.

GENETIC SCHEDULING OF TASK GRAPHS. INTERNATIONAL JOURNAL OF ELECTRONICS 77 (4): 401-415 OCT 1994.

GAP - A GENETIC ALGORITHM APPROACH TO OPTIMIZE 2-BIT DECODER PLAS. INTERNATIONAL JOURNAL OF ELECTRONICS 76 (1): 99-106 JAN 1994.

The architecture of a highly reconfigurable RISC dataflow array processor. INTERNATIONAL JOURNAL OF ELECTRONICS 83 (4): 493-518 OCT 1997.

Scheduling and allocation in high-level synthesis using stochastic techniques. MICROELECTRONICS JOURNAL 27 (8): 693-712 NOV 1996.

High-level synthesis from purely behavioral descriptions. COMPUTER SYSTEMS SCIENCE AND ENGINEERING 11 (5): 259-273 SEP 1996.

Formal synthesis of VLSI layouts from algorithmic specifications. COMPUTER SYSTEMS SCIENCE AND ENGINEERING 11 (2): 67-81 MAR 1996.

Timing driven genetic placement. COMPUTER SYSTEMS SCIENCE AND ENGINEERING 14 (1): 3-14 JAN 1999.

UNIVERSAL ALPHA-A LANGUAGE FOR VLSI DESIGN AUTOMATION. IEEE CIRCUITS AND DEVICES MAGAZINE, 8-14 SEP 1986.

A CMOS CELL FOR PARALLELLY LOADABLE COUNTERS. INTERNATIONAL JOURNAL OF ELECTRONICS, 62 (6): 867-871 NOV 1987.

BIT-SLICE MICROPROCESSOR-BASED COMMUNICATIONS DECODER. MICROPROCESSORS AND MICROSYSTEMS 11 (10): 527-533 DEC 1987.

A GENERAL REAL-TIME DECODER BASED ON AMD2900 DEVICES. MICROPROCESSING AND MICROPROGRAMMING 22 (2): 97-113 FEB 1988.

CAD TOOL FOR THE AUTOMATIC-GENERATION OF MICROPROGRAMS. MICROPROCESSORS AND MICROSYSTEMS 12 (8): 463-470 OCT 1988.

AUTOMATIC WEINBERGER ARRAY SYNTHESIS FROM UAHPL DESCRIPTION. INTERNATIONAL JOURNAL OF ELECTRONICS 69 (2): 211-224 AUG 1990.

STATE MACHINE SYNTHESIS WITH WEINBERGER ARRAYS. INTERNATIONAL JOURNAL OF ELECTRONICS 71 (1): 1-12 JUL 1991.

PCB LAYOUT GENERATION FROM RTL SPECIFICATIONS. INTERNATIONAL JOURNAL OF ELECTRONICS 72 (1): 1-10 JAN 1992.

INTEGRATING UAHPL-DA SYSTEMS WITH VLSI DESIGN TOOLS TO SUPPORT VLSI DA COURSES. IEEE TRANSACTIONS ON EDUCATION 35 (4): 321-330 NOV 1992.

Topology design of switched enterprise networks using a fuzzy simulated evolution algorithm. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (3-4): 327-340 JUN-AUG 2002.

VLSI LAYOUT GENERATION OF A PROGRAMMABLE CRC CHIP. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 39 (4): 911-916 NOV 1993.

DESIGNING ASICS WITH UAHPL. IEEE CIRCUITS AND DEVICES MAGAZINE 11 (2): 14-24 MAR 1995.

HARDWARE DESIGN AND VLSI IMPLEMENTATION OF A BYTE-WISE CRC GENERATOR CHIP. IEEE CIRCUITS AND DEVICES MAGAZINE 11 (2): 14-24 MAR 1995.

EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 3 (2): 254-263 JUN 1995.

VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995.

(2007) Effective Parallelization of Stochastic Evolution. In: ISDA'07 Conference. (Unpublished)

(2006) Parallel Stochastic Evolution Algorithms for Constrained Multiobjective Optimization. In: SNPD'07. (Unpublished)

Scheduling and allocation in high-level synthesis using stochastic techniques. MICROELECTRONICS JOURNAL 27 (8): 693-712 NOV 1996.

Timing influenced general-cell genetic floorplanner. MICROELECTRONICS JOURNAL 28 (2): 151-166 FEB 1997.

CMOS/BiCMOS mixed design using tabu search. ELECTRONICS LETTERS 34 (14): 1395-1396 JUL 9 1998.

A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999.

Fuzzy genetic algorithm for floorplanning. ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING AND COMMUNICATIONS 8 (3): 145-153 SEP 2000.

Evolutionary algorithms, simulated annealing and tabu search: a comparative study. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 14 (2): 167-181 APR 2001.

Parallelizing Tabu Search on a Cluster of HeterogeneousWorkstations. JOURNAL OF HEURISTICS 8 (3): 277-304 MAY 2002.

Fuzzy evolutionary hybrid metaheuristic for network topology design. LECTURE NOTES IN COMPUTER SCIENCE 1993: 400-415 2001.

QoS-driven multicast tree generation using tabu search. COMPUTER COMMUNICATIONS 25 (11-12): 1140-1149 Sp. Iss. SI JUL 1 2002.

Tabu searchbased circuit optimization. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (3-4): 357-368 JUN-AUG 2002.

Topology design of switched enterprise networks using a fuzzy simulated evolution algorithm. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (3-4): 327-340 JUN-AUG 2002.

A simulated evolution approach to task-matching and scheduling in heterogeneous computing environments. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (5): 491-500 SEP 2002.

Simulated evolution for timing and low power VLSI standard cell placement. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 16 (5-6): 407-423 AUG-SEP 2003.

A FUZZY EVOLUTIONARY ALGORITHM FOR TOPOLOGY DESIGN OF CAMPUS NETWORKS. ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 29 (2B): 195-212 OCT 2004.

(2005) Evolutionary algorithms for state justification in sequential automatic test pattern generation.

(2005) A Parallel Tabu Search Algorithm for Optimizing Multiobjective VLSI Placement. LECTURE NOTES IN COMPUTER SCIENCE 3483: 587-595 2005.

(2006) Evolutionary Algorithms for VLSIMultiobjective Netlist Partitioning. ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING AND COMMUNICATIONS 13 (1): 15-21 MAR 2005.

SimE/TS fuzzy hybrid for multiobjective VLSI placement. ELECTRONICS LETTERS 42 (6): 364-365 MAR 16 2006.

(2006) FAST FUZZY FORCE-DIRECTED/SIMULATED EVOLUTION METAHEURISTIC FOR MULTIOBJECTIVE VLSI CELL PLACEMENT. Arabian Journal for Science and Engineering Submitted Jun 2006.

Designing Cellular Mobile Networks Using Non{Deterministic Iterative Heuristics. Journal of Applied Soft Computing submitted Oct 2006.

A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.

Exploring Asynchronous MMC based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster-of-Workstations. Journal of CLUSTER COMPUTING: SUBMITTED: SEPT 2007.

Trends in Internet Usage & its Social Effects in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

“Summary Report” Structure of National IT Plan for Saudi Arabia. In: Department of Computer Engineering, KFUPM.

Tabu Search Based Circuit Optimization. In: Department of Computer Engineering, KFUPM.

Exploring Asynchronous MMC Based Parallel SA Schemes for Multiobjective Cell-Placement on a Cluster of Workstations. Cluster Computing, The Journal of Networks, Software Tools and Applications. ISSN ISSN: 1386-7857 (print version), ISSN: 1573-7543 (electronic version) (Submitted)

(2007) Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. Journal of Mathematical Modelling and Algorithms (JMMA), 6 (3). pp. 433-454. ISSN 1570-1166 (Print) 1572-9214 (Online)

(2005) Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm. In: International Symposium on Circuits and Systems, (ISCAS 05), Kobe, Japan.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: International Symposium on Circuits and Systems, (ISCAS 06), Kos, Greece.

Strategy Planning for Higher Education Project Horizon. In: King Fahd University of Petroleum & Minerals.

The Aafaq Web. In: Department of Computer Engineering, KFUPM.

(2001) Iterative Heuristics for Timing & low power VLSI standard cell placement. In: Unknown. (Unpublished)

Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

The COE Department. In: Computer Engineering Department, KFUPM.

Transmission Media. In: Department of Computer Engineering, KFUPM.

Use and Effect of Internet in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

WWW & E-Commerce. In: Department of Computer Engineering, KFUPM.

(2006) Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. In: International Parallel and Distributed Processing Symposium, April, 2006, Rhodes Island, Greece.

(2005) Comparative Evaluation of Parallelization Strategies for Evolutionary and Stochastic Heuristics. In: Genetic and Evolutionary Computation Conference (GECCO-2005),, 25-29 June, 2005, Washington D.C. , USA.

(2005) Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning. In: Unknown.

FUZZIFIED SIMULATED EVOLUTION ALGORITHM FOR MULTI-OBJECTIVE OPTIMIZATION OF COMBINATIONAL LOGIC CIRCUITS. In: Computer Engineering Department, KFUPM.

Fast Fuzzy Force-Directed/Simulated Evolution Metaheuristic for Multiobjective VLSI Cell Placement. In: Department of Computer Engineering, KFUPM.

(2001) Modern Iterative Algorithms and thier Applications in Computer Engineering. In: Book.

EFFICIENT COMBINATIONAL CIRCUITS DESIGN THROUGH FUZZIFIED ANT COLONY OPTIMIZATION ALGORITHM. In: Computer Engineering Department, KFUPM.

Computer Engineering Department Research Profile. In: Computer Engineering Department, KFUPM.

Information Technology Center (ITC) Services and Projects. In: Supporting excellence via technology, KFUPM.

CCSE PAST & PRESENT STANDING. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

(2003) Iterative Computer Algorithms with Applications in Engineering-Chapter 2: Partitioning. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

Chapter 1: Introduction to VLSI Physical Design. In: King Fahd University of Petroleum & Minerals.

Automating Your Schedule. In: Special Mini Talk/Demo for 993 Summer, Dhahran, Saudi Arabia.

An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation. In: An Iterative Heuristic for State Justification in, Dhahran, Saudi Arabia.

Area-Time Optimal Adder with Relative Placement Generator. In: Area-Time Optimal Adder with Relative Placement Generator.

Iterative Computer Algorithms: and their applications in engineering. In: Special Talk for Motorola CAD Group,.

(2001) An Iterative Heuristic for State Justi�cation in Sequential Automatic Test Pattern Generation. Genetic and Evolutionary Computation Conference (GECCO).

(2001) An Evolutionary Meta-Heuristic for State Justification in Sequential Automatic Test Pattern Generation. International Joint INNS-IEEE Conference on Neural Networks (IJCNN). pp. 767-772.

(2000) A Parallel Tabu Search Algorithm for VLSI Standard-Cell Placement. In: IEEE International Symposium on Circuits and Systems'', Geneva.

(2000) Fuzzy Simulated Evolution Algorithm for Topology Design on Campus Networks. In: IEEE Congress on Evolutionary Computation, San Diego, USA.

(1999) Fuzzy Simulated Evolution Algorithm for Multiobjective Optimization of VLSI Placement. In: IEEE Congress on Evolutionary Computation, Washington DC.

(1995) Timing Influenced General-Cell Genetic Floorplanner. In: Asia and South-Pacific Design Automation Conference, ASP-DAC'95, Japan.

(1995) Timing Influenced Force Directed Floorplanning. In: European Design Automation Conference with Euro-VHDL, Euro-DAC'95, Brighton.

(1995) A Novel Technique for Fast Multiplication. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1995) Timing Driven Genetic Algorithm for Placement. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1995) Performance Driven Standard-cell Placement Using the Genetic Algorithm. In: Fifth Great Lakes Symposium on VLSI, GLSVLSI'95, Buffalo, USA.

(1995) Loop based scheduling for high level synthesis. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1994) Design of a Cell Library for Formal High-level Synthesis. In: IEEE Melecon'94.

(1994) ASIC Design with AHPL. In: IEEE Melecon'94.

(1992) High Level Synthesis of Controllers for Communication Protocols. In: Second Great Lakes Symposium on VLSI, GLSVLSI'92, Kalamazoo.

(1992) VLSI Implementation of Controllers for Communication Protocols from their Petri Net Models. In: IEEE International Symposium on Circuits and Systems, California.

(1991) A State Machine Synthesizer with Weinberger Arrays. In: The IEEE Pacific RIM Conference, Victoria, Canada.

(1989) A Systolic Algorithm for VLSI Design of a Rate Viterbi Decoder. In: IEEE Melecon'89, Portugal.

(1994) GSA: Scheduling and Allocation using Genetic Algorithm. In: European Design Automation Conference with Euro-VHDL, Euro-DAC'94, Grenoble.

(1998) Tabu Search Based Circuit Optimization. In: Great Lakes Symposium on VLSI, GLSVLSI'98, SW Louisiana.

(1998) Performance and Interface Buffer Size Driven Behavioral Partitioning for Embedded Systems. In: 9th International Workshop on Rapid Systems Prototyping, IEEE Computer Society Sponsored, Leuven, Belgium.

(1998) Buffer Size Driven Partitioning for HW/SW Co-Design. In: IEEE International Conference on Computer Design, ICCD'98, Austin, USA.

(1999) A High-Performance Hardware-EÆcient Memory Allocation Technique and Design. In: IEEE International Conference on Computer Design, ICCD'99, Austin, USA.

(2001) Task Matching and Scheduling in Heterogeneous Systems Using Simulated Evolution. In: 10th Heterogeneous Computing Workshop in conjunction with IPDPS 2001, San Francisco.

(2001) Fuzzy Evolutionary Hybrid Metaheuristic for Network Topology Design. In: International Conference on Evolutionary Multi-Criterion Optimization, EMO'01, ETH Zurich, Switzerland (A Springer Publication).

(2001) Adaptive Bias Simulated Evolution Algorithm for Placement. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) A Fast Constructive Algorithm For Fixed Channel Assignment Problem. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) Fuzzy Evolutionary Algorithm for VLSI Placement, (Spector, L., E. Goodman, A. Wu, W. B. Langdon, H.-M. Voigt, M. Gen, S. Sen, M. Dorigo, S. Pezeshk, M. Garzon, and E. Burke, editors). In: Proceedings of the Genetic and Evolutionary Computation Conference, GECCO-2001, San Francisco, CA.

(2001) An Evolutionary Algorithm for Network Topology Design. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzy Simulated Evolution for Power and Performance Optimization of VLSI Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Iterative Heuristics for Multiobjective VLSI Cell Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. In: IEEE International Conference on Computer Design, ICCD'2001, Austin.

(2002) HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) PERFORMANCE AND LOW POWER DRIVEN VLSI STANDARD CELL PLACEMENT USING TABU SEARCH. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) FUZZY AGGREGATING FUNCTIONS FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE International Conference on Fuzzy Systems', Honolulu, Hawaii, USA.

(2002) FUZZY BIASLESS SIMULATED EVOLUTION FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2003) Parallel Tabu Search in a Heterogeneous Environment. In: Proceedings of 17th International Parallel & Distributed Processing Symposium.

(2003) GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Simulated Evolution Algorithm For Multiobjective VLSI Netlist Bi-Partitioning. In: IEEE International Symposium on Circuits and Systems', Bangkok, Thailand.

(2003) AREA-TIME OPTIMAL ADDER WITH RELATIVE PLACEMENT GENERATOR. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part I: Enumerative Techniques. In: IEEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part II: Iterative Techniques. In: EEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING. In: IEEE International Symposium on Circuits and Systems, Sharjah, UAE.

(2003) Digital Circuit Design Through Simulated Evolution (SimE). In: IEEE Congress on Evolutionary Computation (CEC),, Canberra, Australia.

(2003) A Modified Ant Colony Algorithm for Evolutionary Design of Digital Circuits. In: IEEE Congress on Evolutionary Computation, Canberra, Australia.

(2003) Ant Colony Algorithm for Evolutionary Design of Arithmetic Circuits. In: Proceedings of the 15th International Conference, Cairo, Egypt.

(2004) FAST FORCE-DIRECTED/SIMULATED EVOLUTION HYBRID FOR MULTIOBJECTIVE VLSI CELL PLACEMENT. In: IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada.

(2004) Fuzzified Ant Colony Optimization Algorithm for Efficient Combinational Circuits Synthesis. In: IEEE Congress on Evolutionary Computation (CEC),, Portland Oregon, USA.

(2004) Enhanced Simulated Evolution Algorithm For Digital Circuit Design Yielding Faster Execution in a Larger Solution Space. In: IEEE Congress on Evolutionary Computation (CEC),, Portland, Oregon, USA.

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. In: International Symposium on Circuits and Systems, (ISCAS 05),, Kobe, Japan.

(2005) Multiobjective VLSI Cell Placement using Distributed Genetic Algorithm. In: Genetic and Evolutionary Computation Conference (GECCO-2005), Washington D.C. , USA.

(2005) Efficient Static Compaction Techniques for Sequential Circuits based on Reverse Order Restoration Based and Test Relaxation. In: Proceedings of the 14th Asian Test Symposium (ATS ’05), Kolkata, India.

(2006) An Enhanced Estimator to Multi-objective OSPF WeightSetting Problem. In: Proceedings of 2006 IEEE/IFIP Network Operations & Management Symposium (NOMS 2006),, Vancouver, Canada.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: Proceedings of 2006 International Symposium in Circuits and Systems, pages 4615-4618, (ISCAS 2006), Island of Kos, Greece.

(2006) Finite State Machine State Assignment for Area and Power Minimization. In: Proceedings of 2006 International Symposium in Circuits and Systems, (ISCAS 2006), Island of Kos, Greece.

(2006) A Heuristics Based Approach for Cellular Mobile Network Planning. In: The International Wireless Communications and Mobile Computing Conference (IWCMC06), Vancouver, Canada.

(2007) Algorithm for Parallel Inverse Halftoning using Partitioning of Look-Up Table (LUT). IEEE Symposium on Circuits and Systems (ISCAS). (Submitted)

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. IEEE Symposium on Circuits and Systems (ISCAS).

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. In: IEEE Symposium on Circuits and Systems (ISCAS) 2005, Kobe, Japan.

(1992) INTEGRATING UAHPL-DA SYSTEMS WITH VLSI DESIGN TOOLS TO SUPPORT VLSI DA COURSES. IEEE TRANSACTIONS ON EDUCATION 35 (4): 321-330 NOV 1992 (JZ981). ISSN 0018-9359

(2006) Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 25 (11): 2556-2564 NOV 2006.

(2006) A Parallel Algorithm for Inverse Halftoning and its Hardware. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.

(2003) Fuzzy simulated evolution algorithm for VLSI cell placement. COMPUTERS & INDUSTRIAL ENGINEERING 44 (2): 227-247 FEB 2003. ISSN 0360-8352

(2006) Evolutionary algorithms for VLSI multi-objective netlist partitioning. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 19 (3): 257-268 APR 2006. ISSN 0952-1976