Formal synthesis of VLSI layouts from algorithmic specifications

Formal synthesis of VLSI layouts from algorithmic specifications. COMPUTER SYSTEMS SCIENCE AND ENGINEERING 11 (2): 67-81 MAR 1996.

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Abstract

Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of translating the abstract behavioural representation. In this paper we present a formal approach for high level synthesis. This formal high level syntesis system uses recursive algorithms to model the behaviour to be synthesized. These algorithms can be mathematically verified for correctness before begin subjected to the task of translation. As a case study, the modelling and synthesis of VLSI layouts for matrix-matrix multipliers is discussed. Keywords: Formal synthesis, VLSI layous, Algorithmic specifications, high level synthesis

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AbdulRahman
Date Deposited: 15 Mar 2008 06:06
Last Modified: 01 Nov 2019 13:23
URI: https://eprints.kfupm.edu.sa/id/eprint/367