Parallel Algorithm for Hardware Implementation of Inverse Halftoning

(2005) Parallel Algorithm for Hardware Implementation of Inverse Halftoning. In: IEEE Symposium on Circuits and Systems (ISCAS) 2005, Kobe, Japan.

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Item Type: Conference or Workshop Item (Lecture)
Subjects: Computer
Department: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: UMAIR FAROOQ SIDDIQI
Date Deposited: 08 Dec 2007 07:47
Last Modified: 01 Nov 2019 13:22
URI: https://eprints.kfupm.edu.sa/id/eprint/63