Thesis

(2007) Parallel Algorithms for Look-Up Table (LUT) Inverse Halftoning. Masters thesis, King Fahd University of Petroleum & Minerals, Dhahran.

(2006) A framework for a reliable and fault-tolerant network management architecture. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Ant colony multi-optimization algorithm for circuit bi-partitioning. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Design of a graphical user interface to augment a telerobotic stereo-vision system. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) FSM state-assignment for area, power and testability using non-deterministic evolutionary heuristics. Masters thesis, King Fahd University of Petroleum and Minerals.

(2004) Test set compaction for sequential circuits based on test relaxation. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Measurement based comparison between VoIPoMPLS and VoIP using software routers. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Content-aware congestion control over MPLS networks for multimedia transmission. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Extensions to XML-based network management. Masters thesis, King Fahd University of Petroleum and Minerals.

(2006) Power based scheduling algorithms for WCDMA networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(2003) Memory performance evaluation of high throughput servers. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) Signaling traffic analysis of GSM authentication protocols. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) Evolution based scheduling of precedence computations with communication costs. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Optimization of mixed CMOS/BiCMOS circuits using tabu search. Masters thesis, King Fahd University of Petroleum and Minerals.

(2003) Memory performance evaluation of high throughput servers. Masters thesis, King Fahd University of Petroleum and Minerals.

(1999) A Parallel Tabu search algorithm for VLSI standard cell placement. Masters thesis, King Fahd University of Petroleum and Minerals.

(2002) An Efficient test-pattern relaxation technique for synchronous sequential circuits. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) QoS-driven multicast routing algorithms. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) A C-Based high level synthesis system. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) Experimenting with evolutionary meta-heuristics for state justification in sequential ATPG. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Fault characterization and testability considerations in multi-valued logic circuits. Masters thesis, King Fahd University of Petroleum and Minerals.

(2003) Modified ANT colony algorithm for combinational logic circuits design. Masters thesis, King Fahd University of Petroleum and Minerals.

(2004) Performance analysis and modeling of disk I/O subsystem in high throughput servers. Masters thesis, King Fahd University of Petroleum and Minerals.

(2003) Digital circuit design through simulated evolution. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) HCORDIC: a high-performance cordic algorithm. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) A new traffic control scheme for ATM networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) A Framework for yield enhancement of processor arrays. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) Timing driven placement algorithm for standard-cell design. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) Dataflow processor for back propagation nueral networks: architecture and performance evaluation. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) Hardware specific optimization on RTL description. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) SELF-MAP: stochastic evolution LUT-FPGA technology mapper. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) Quality of service routing. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) Iterative algorithms for timing and low power driven VLSI standard-cell placement. Masters thesis, King Fahd University of Petroleum and Minerals.

(1993) Back-end design of a formal high level synthesis system. Masters thesis, King Fahd University of Petroleum and Minerals.

(1993) Priority-based scheduling and evaluation of precedence graphs with communication times. Masters thesis, King Fahd University of Petroleum and Minerals.

(2004) Designing a self-timed arithmetic logic unit. Masters thesis, King Fahd University of Petroleum and Minerals.

(1999) Topology design of enterprise networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Fuzzy logic based FPGA routing. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) Genetic algorithm for timing influenced floorplanning of VLSI designs. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) An Ethernet bridge with packet filtering and statistics collection capabilities. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) A Two-dimensional geometric-shapes-based compression scheme for deterministic testing of systems-on-a-chip. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) A framework for the VLSI implementation of systolic tree based data structures. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) Development of a congestion control scheme for ATM networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Evaluation and comparison of Ingternet firewalls. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) Evaluation of pipelined switch architectures for ATM networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) Design and analysis of a fault-tolerant switch for B-ISDN. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) A Formal VLSI parallel description and design environment. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Fuzzy simulated evolution algorithm for VLSI cell placement. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) Intermediate forms in high-level synthesis. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) Design and analysis of a high-performance fault-tolerant ATM network. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) On the synthesis and optimization of MVL functions. Masters thesis, King Fahd University of Petroleum and Minerals.

(1996) A Novel fast packet switch architecture for ATM networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(1993) Built-in self test logic for a histogrammer memory chip. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) A Hardware model of an expandable RSA cryptographic system. Masters thesis, King Fahd University of Petroleum and Minerals.

(1998) A virtual distributed computing system. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) Timing driven floorplanning. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) The Cognitive self-structuring connectionist machine. Masters thesis, King Fahd University of Petroleum and Minerals.

(1993) An area efficient FPGA: Design using non volatile RAM. Masters thesis, King Fahd University of Petroleum and Minerals.

(2001) Multicast routing protocol with partial flooding for ad hoc wireless networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(2005) Ant colony multi-optimization algorithm for circuit bi-partitioning. Masters thesis, King Fahd University of Petroleum and Minerals.

(2006) A framework for a reliable and fault-tolerant network management architecture. Masters thesis, King Fahd University of Petroleum and Minerals.

(1994) Design and modeling of a real-time RISC processor in VHDL. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) Fuzzy genetic algorithm for VLSI floorplan design. Masters thesis, King Fahd University of Petroleum and Minerals.

(2002) Evolutionary techniques for multi-objective VLSI netlist partitioning. Masters thesis, King Fahd University of Petroleum and Minerals.

(1997) Organization of parallel memories. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) AutoVLSI system: a layout system for general-cell VLSI design. Masters thesis, King Fahd University of Petroleum and Minerals.

(1995) Reliability of modular fault-tolerant hypercube networks. Masters thesis, King Fahd University of Petroleum and Minerals.

(2000) Performance of Adaptive Admission/Congestion Control Policies on a Hybrid MC-CDMA/TDMA Integrated Multimedia Networks. PhD thesis, Concordia Univesrity.

(1993) Back-End Design of a Formal High Level Synthesis System. Masters thesis, KING FAHD UNIVERSITY OF PETROLEUM & MINERALS.

(1993) An Area Efficient FPGA: Design using Non-Volatile RAM. Masters thesis, KING FAHD UNIVERSITY OF PETROLEUM & MINERALS.

(1998) Hardware Model of an Expandable RSA Cryptographic System. Masters thesis, King Fahd University of Petroleum and Minerals (KFUPM).

(2007) A Stochastic Approach To Solving The Weight Setting Problem in OSPF Networks. Masters thesis, KFUPM.

(2002) New Hardware Algorithms and Designs for Montgomery Modular Inverse Computation in Galois Fields GF(p) and GF(2n). PhD thesis, Oregon State University.

(1998) A Hardware Model of an Expandable RSA Cryptogrsphic System. Masters thesis, King Fahd University of Petroleum and Minerals (KFUPM).

Article

(2008) Efficient Test Compression Technique Based on Block Merging. IET Comput. Digit. Tech., 2 (5). pp. 327-335.

(2008) Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning. Arabian Journal of Science and Engineering (AJSE).

(2000) Fuzzy simulated evolution algorithm for topology design of campusnetworks. Evolutionary Computation, 2000. Proceedings of the 2000 Congress on, 1.

(1995) Performance driven standard-cell placement using the geneticalgorithm. VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on, 1.

(2003) Parallel tabu search in a heterogeneous environment. Parallel and Distributed Processing Symposium, 2003. Proceedings. International, 1.

(2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

(2004) Thermal management of high power transformer in different outdoor environment conditions. Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety conference, 1.

Timing influenced general-cell genetic floorplanner. Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International conference Hardware Description Languages, 1.

(2003) A new static differential CMOS logic with superior low power performance. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 2.

(2004) A class-based clustering static compaction technique for combinational circuits. Microelectronics, 2004. ICM 2004 Proceedings. The 16th International conference, 1.

(2003) High performance elliptic curve GF(2/sup k/) cryptoprocessor architecture for multimedia. Multimedia and Expo, 2003. ICME '03. Proceedings. 2003 International conference, 3.

(1992) High level synthesis of controllers for communication protocols. Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on, 4.

(2006) Adaptive QoS-Based Scheduler for 4G CDMA Wireless Networks. Information and Communication Technologies, 2006. ICTTA '06. 2nd, 2.

(1995) Designing ASICs with UAHPL. Circuits and Devices Magazine, IEEE, 11.

(2005) An adaptive load-balancing approach to XML-based network management using JPVM. Networks, 2005. Jointly held with the 2005 IEEE 7th Malaysia International conference Communication., 2005 13th IEEE International conference, 1.

(2003) GF(2 K) elliptic curve cryptographic processor architecture based n bit level pipelined digit serial multiplication. Computer Systems and Applications, 2003. Book of Abstracts. ACS/IEEE International conference, 1.

(2003) Analytic model for MPEG-4 and H.263 encoded video traces. Computer Systems and Applications, 2003. Book of Abstracts. ACS/IEEE International conference, 1.

(2004) Enhanced simulated evolution algorithm for digital circuit design yielding faster execution in a larger solution space. Evolutionary Computation, 2004. CEC2004. Congress on, 2.

(2004) Minimum traffic inter-BS SHO boundary selection algorithm for CDMA-based wireless networks. Radio and Wireless Conference, 2004 IEEE, 1.

(2006) Evaluating parallel simulated evolution strategies for VLSI cell placement. Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, 1.

(2003) Efficient scalable hardware architecture for Montgomery inverse computation in GF(p). Signal Processing Systems, 2003. SIPS 2003. IEEE Workshop on, 1.

(2001) Adaptive bias simulated evolution algorithm for placement. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 5.

(1999) Fuzzy simulated evolution algorithm for multi-objectiveoptimization of VLSI placement. Evolutionary Computation, 1999. CEC 99. Proceedings of the 1999 Congress on, 1.

(1995) Hardware design and VLSI implementation of a byte-wise CRCgenerator chip. Consumer Electronics, IEEE Transactions on, 41.

(2004) Fast force-directed/simulated evolution hybrid for multiobjective VLSI cell placement. Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, 5.

(1998) Tabu search based circuit optimization. VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on, 1.

(2001) A new and fast frequency response estimation technique for noisysystems. Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar conference, 2.

(2002) HPTS: heterogeneous parallel tabu search for VLSI placement. Evolutionary Computation, 2002. CEC '02. Proceedings of the 2002 Congress on, 1.

(2002) Fuzzy aggregating functions for multiobjective VLSI placement. Fuzzy Systems, 2002. FUZZ-IEEE'02. Proceedings of the 2002 IEEE International conference, 2.

(2006) Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 1.

(1995) Timing influenced force directed floorplanning. Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European, 1.

(2001) Iterative heuristics for multiobjective VLSI standard cellplacement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 3.

(1995) Timing driven genetic algorithm for standard-cell placement. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

(2006) A Study on Network Sharing and Radio Resource Management in 3G and Beyond Mobiles Wireless Networks Supporting Heterogeneous Traffic. Information and Communication Technologies, 2006. ICTTA '06. 2nd, 2.

(1999) An expandable Montgomery modular multiplication processor. Microelectronics, 1999. ICM '99. The Eleventh International conference, 1.

(2003) Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

(2003) High radix parallel architecture for GF(p) elliptic curve processor. Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International conference, 2.

(1995) Loop based scheduling for high level synthesis. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

(2006) Novel Peak Detection Algorithms for Pileup Minimization in Gamma Ray Spectroscopy. Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE, 1.

(2006) Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine. Microelectronics, 2006. ICM '06. International conference, 1.

(1999) A high-performance hardware-efficient memory allocation techniqueand design. Computer Design, 1999. (ICCD '99) International conference, 1.

(2001) Fuzzified iterative algorithms for performance driven low powerVLSI placement. Computer Design, 2001. ICCD 2001. Proceedings. 2001 International conference, 1.

(2004) On test vector reordering for combinational circuits. Microelectronics, 2004. ICM 2004 Proceedings. The 16th International conference, 1.

(2006) On Optimizing Backoff Procedure to Enhance Throughput and Fairness For Wireless LANs. Information and Communication Technologies, 2006. ICTTA '06. 2nd, 2.

(2001) Detection of helicopters using neural nets. Instrumentation and Measurement, IEEE Transactions on, 50.

(2003) A hybrid test compression technique for efficient testing of systems-on-a-chip. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 2.

(2007) Packet Reservation Multiple Access (PRMA) with Random Contention. Computer Systems and Applications, 2007. AICCSA '07. IEEE/ACS International conference, 1.

(2001) An evolutionary meta-heuristic for state justification insequential automatic test pattern generation. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(2005) Performance of Heterogeneous Traffic in Roaming Based Sharing Multi-Operator WCDMA Networks. Wireless Communication Systems, 2005. 2nd International Symposium on, 1.

(2003) A modified ant colony algorithm for evolutionary design of digital circuits. Evolutionary Computation, 2003. CEC '03. The 2003 Congress on, 1.

(2003) Unsupervised histogram based color image segmentation. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 1.

(2006) DFT for controlled-impedance I/O buffers. Design Automation Conference, 2006 43rd ACM/IEEE, 1.

(2003) Reliability and fault tolerance based topological optimization of computer networks - part I: enumerative techniques. Communications, Computers and signal Processing, 2003. PACRIM. 2003 IEEE Pacific Rim conference, 2.

(2004) Short-term hourly load forecasting using abductive networks. Power Systems, IEEE Transactions on, 19.

(2003) General iterative heuristics for VLSI multiobjective partitioning. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

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(2006) Skin Detection using a Markov Random Field and a New Color Space. Image Processing, 2006 IEEE International conference, 1.

(2005) Should Illinois-scan based architectures be centralized or distributed? Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on, 1.

(2006) Finite state machine state assignment for area and power minimization. Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 1.

(2003) Reliability and fault tolerance based topological optimization of computer networks - part II: iterative techniques. Communications, Computers and signal Processing, 2003. PACRIM. 2003 IEEE Pacific Rim conference, 2.

(2005) A Prioritized Uplink Call Admission Control Algorithm for 3G WCDMA Cellular Systems with Multi-Services. 3G and Beyond, 2005 6th IEE International conference, 1.

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(2006) SimE/TS fuzzy hybrid for multiobjective VLSI placement. Electronics Letters, 42.

(2003) An efficient test relaxation technique for synchronous sequential circuits. VLSI Test Symposium, 2003. Proceedings. 21st, 1.

(1993) VLSI layout generation of a programmable CRC chip. Consumer Electronics, IEEE Transactions on, 39.

An Enhanced Estimator to Multi-objective OSPF Weight Setting Problem. Network Operations and Management Symposium, 2006. NOMS 2006. 10th IEEE/IFIP, 1.

(2003) Digital circuit design through simulated evolution (SimE). Evolutionary Computation, 2003. CEC '03. The 2003 Congress on, 1.

(2000) A parallel tabu search algorithm for VLSI standard-cell placement. Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, 2.

(2001) Fuzzy simulated evolution for power and performance optimization ofVLSI placement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(1996) Remote valve controller provides precise positioning of processcontrol valves. Southeastcon '96. 'Bringing Together Education, Science and Technology'., Proceedings of the IEEE, 1.

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(2002) Performance and low power driven VLSI standard cell placement usingtabu search. Evolutionary Computation, 2002. CEC '02. Proceedings of the 2002 Congress on, 1.

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(1992) Integrating UAHPL-DA systems with VLSI design tools to support VLSIDA courses. Education, IEEE Transactions on, 35.

(2006) Interconnect-Efficient LDPC Code Design. Microelectronics, 2006. ICM '06. International conference, 1.

(2001) Bit-level pipelined digit serial GF(2m) multiplier. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 4.

(2006) Performance improvement of dynamic source routing protocol the mobility effect of nodes in cache management. Wireless and Optical Communications Networks, 2006 IFIP International conference, 1.

(2001) An evolutionary algorithm for network topology design. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 1.

(2004) Fuzzified ant colony optimization algorithm for efficient combinational circuits synthesis. Evolutionary Computation, 2004. CEC2004. Congress on, 2.

(2003) Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 1.

(2003) A static test compaction technique for combinational circuits based on independent fault clustering. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3.

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(2006) A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links. Microelectronics, 2006. ICM '06. International conference, 1.

(2005) Parallel algorithm for hardware implementation of inverse halftoning. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 1.

(2006) An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications. Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International conference, 1.

(2006) A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication. Microelectronics, 2006. ICM '06. International conference, 1.

(2006) Synthesis of MVL Functions - Part I: The Genetic Algorithm Approach. Microelectronics, 2006. ICM '06. International conference, 1.

(2006) Performance analysis of Internet applications over an adaptive IEEE 802.11 MAC architecture. Journal of the Franklin Institute, 343 (4-5). pp. 352-360.

(2006) Adaptive admission/congestion control policies for CDMA-based wireless internet. WIRELESS COMMUNICATIONS AND MOBILE COMPUTING, 6 (1). pp. 1-15.

(2000) A Hybrid TDMA/MC-CDMA System Utilizing Multiuser Detection for Integrated Wireless Networks. IEICE Transactions on Communications, Vol.E8 (6). pp. 1308-1320.

REVIEW OF HIGH-SPEED DIGITAL CMOS CIRCUITS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

Message Concealment Techniques using Image based Steganography. IEEEGCC 2007.

A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design. IEEEGCC 2007.

Reliability based Topological Optimization of Computer Networks - Part II: Iterative Techniques. IEEETEM2003.

Analysis of KFUPM Web Traffic Using Proxy Access Logs. IEEETEM2003.

A Measurement Based Memory Performance Evaluation of Streaming Media Servers. IEEETEM2003.

A METHODOLOGY FOR NETWORK TOPOLOGY DESIGN USING FUZZY EVALUATIONS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

EVOLUTIONARY HEURISTICS FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

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Improving the Classification of Multiple Disorders with Problem Decomposition. JOURNAL OF BIOMEDICAL INFORMATICS, 39 (6): 612-625 DEC 2006.

Prediction of evaporation losses in wet cooling towers. Heat Transfer Engineering, 27(9):86–92, 2006.

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Formal synthesis of VLSI layouts from algorithmic specifications. COMPUTER SYSTEMS SCIENCE AND ENGINEERING 11 (2): 67-81 MAR 1996.

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QoS-driven multicast tree generation using tabu search. COMPUTER COMMUNICATIONS 25 (11-12): 1140-1149 Sp. Iss. SI JUL 1 2002.

Tabu searchbased circuit optimization. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (3-4): 357-368 JUN-AUG 2002.

Topology design of switched enterprise networks using a fuzzy simulated evolution algorithm. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (3-4): 327-340 JUN-AUG 2002.

A simulated evolution approach to task-matching and scheduling in heterogeneous computing environments. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 15 (5): 491-500 SEP 2002.

Simulated evolution for timing and low power VLSI standard cell placement. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 16 (5-6): 407-423 AUG-SEP 2003.

A FUZZY EVOLUTIONARY ALGORITHM FOR TOPOLOGY DESIGN OF CAMPUS NETWORKS. ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 29 (2B): 195-212 OCT 2004.

(2005) Evolutionary algorithms for state justification in sequential automatic test pattern generation.

(2005) A Parallel Tabu Search Algorithm for Optimizing Multiobjective VLSI Placement. LECTURE NOTES IN COMPUTER SCIENCE 3483: 587-595 2005.

(2006) Evolutionary Algorithms for VLSIMultiobjective Netlist Partitioning. ENGINEERING INTELLIGENT SYSTEMS FOR ELECTRICAL ENGINEERING AND COMMUNICATIONS 13 (1): 15-21 MAR 2005.

SimE/TS fuzzy hybrid for multiobjective VLSI placement. ELECTRONICS LETTERS 42 (6): 364-365 MAR 16 2006.

(2006) FAST FUZZY FORCE-DIRECTED/SIMULATED EVOLUTION METAHEURISTIC FOR MULTIOBJECTIVE VLSI CELL PLACEMENT. Arabian Journal for Science and Engineering Submitted Jun 2006.

Designing Cellular Mobile Networks Using Non{Deterministic Iterative Heuristics. Journal of Applied Soft Computing submitted Oct 2006.

A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.

Exploring Asynchronous MMC based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster-of-Workstations. Journal of CLUSTER COMPUTING: SUBMITTED: SEPT 2007.

Exploring Asynchronous MMC Based Parallel SA Schemes for Multiobjective Cell-Placement on a Cluster of Workstations. Cluster Computing, The Journal of Networks, Software Tools and Applications. ISSN ISSN: 1386-7857 (print version), ISSN: 1573-7543 (electronic version) (Submitted)

(2007) Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. Journal of Mathematical Modelling and Algorithms (JMMA), 6 (3). pp. 433-454. ISSN 1570-1166 (Print) 1572-9214 (Online)

(1997) The Pitfalls of Necessary Assignments. Fourth International Test Synthesis Workshop.

(1998) A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. 32nd Design Automation Congference. pp. 625-631.

(2004) Efficient Scalable VLSI Architecture for Montgomery Inversion in GF(p). Integration, the VLSI Journal, 37 (2). pp. 103-120. ISSN 0167-9260

(2005) Efficient unified Montgomery inversion with multi-bit shifting. IEE Proceedings Computers and Digital Techniques, 152 (4). pp. 489-498. ISSN 1350-2387

(2006) Merging GF(p) Elliptic Curve Point Adding and Doubling on Pipelined VLSI Cryptographic ASIC Architecture. International Journal of Computer Science and Network Security (IJCSNS), 6 (3A). pp. 44-52. ISSN 1738-7906

(2006) Highly Efficient Elliptic Curve Crypto-Processor with Parallel GF(2m) Field Multipliers. Journal of Computer Science (JCS), 2 (5). pp. 395-400. ISSN 1549-3636

(2006) High Performance Elliptic Curve GF(2m) Crypto-processor. Information Technology Journal (ITJ), 5 (4). pp. 742-748. ISSN 1812-5638

(2006) Fast 160-Bits GF (P) Elliptic Curve Crypto Hardware of High-Radix Scalable Multipliers. International Arab Journal of Information Technology (IAJIT), 3 (4). pp. 342-349. ISSN 1683-3198

(2007) Area Flexible GF(2k) Elliptic Curve Cryptography Coprocessor. International Arab Journal of Information Technology (IAJIT), 4 (1). pp. 1-10.

(2007) PARALLEL COMPUTING PLATFORM FOR EVALUATING LDPC CODES PERFORMANCE. IEEE International Conference on Signal Processing and Communications. pp. 157-160.

(2003) Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits. ACM Transactions on Design Automation of Electronic Systems, 8 (4). pp. 430-459.

(2003) ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS. IEEE International Symposium on Circuits and Systems. V-545 -V-548.

(2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130.

(2007) IMPROVING BER PERFORMANCE OF LDPC CODES BASED ON INTERMEDIATE DECODING RESULTS. IEEE International Conference on Signal Processing and Communications. pp. 1547-1550.

(2003) A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip. 10th IEEE International Conference on Electronics, Circuits and Systems,. pp. 599-602.

(2002) Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 449-452.

(2007) Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering. IET Computers & Digital Techniques, 1 (4). pp. 364-368.

(2006) Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering. IEEE Int. Design and Test Workshop.

(2007) High Speed Hardware Architecture to Compute GF(p) Montgomery Inversion with Scalability Features. IET (IEE) Proceedings Computers and Digital Techniques, 1 (4). pp. 389-396. ISSN 1751-861X

(2007) Efficient utilization of scalable multipliers in parallel to compute GF(p) elliptic curve cryptographic operations. Kuwait Journal of Science & Engineering (KJSE), December 2007, 34 (2). pp. 165-182.

(2001) An Iterative Heuristic for State Justi�cation in Sequential Automatic Test Pattern Generation. Genetic and Evolutionary Computation Conference (GECCO).

(2001) An Evolutionary Meta-Heuristic for State Justification in Sequential Automatic Test Pattern Generation. International Joint INNS-IEEE Conference on Neural Networks (IJCNN). pp. 767-772.

(2001) An Efficient Test Vector Compression Technique Based on Geometric Shapes. 8th IEEE International Conference on Electronics, Circuits and Systems. pp. 1561-1564.

(2006) An Efficient Test Vector Compression Technique Based on Block Merging. IEEE Int. Symp. on Circuits and Systems. pp. 1447-1450.

(2004) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits, 23 (6). pp. 933-940.

(2003) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE International Symposium on Circuits and Systems. V-545 -V-548.

(2007) A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition. 16th IEEE Asian Test Symposium. pp. 91-94.

(2001) A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. 19’th IEEE VLSI Test Symposium (VTS). pp. 54-59.

Book

Youssef, H. COMPUTER NETWORK. ANALOG AND DIGITAL.

Book Section

(1999) A New Hybrid CDMA/TDMA Multiuser Receiver System. In: Wireless Personal Communications: Emerging Technologies for Enhanced Communications. Kluwer Academic Publishers, pp. 111-121.

Conference or Workshop Item

(2007) Coding Erasures with Cooperative Diversity for Wireless ad Hoc networks. In: the Second International Conference on Modeling, Simulation and Applied Optimization (ICMSAO-07), March 24-27, 2007, Abu Dhabi, UAE.

(2007) EQOSA: Energy and QoS Aware MAC for Wireless Sensor Networks. In: ISSPA 2007 International Symposium on Signal Processing and its Applications,, February 12-15, 2007, Sharjah, UAE.

(2006) An Uplink Admission Control for 3G and Beyond Roaming Based Multi-Operator Cellular Wireless Networks with Multi-Services. In: The 4th ACS/IEEE International Conference on Computer Systems and Applications, Sharjah, UAE..

(2006) An Uplink Performance Evaluation for Roaming-Based Multi-Operator WCDMA Cellular Networks. In: The 4th ACS/IEEE International Conference on Computer Systems and Applications.

(2007) Impact of Mobility on Bypass AODV Protocol in Mobile Ad Hoc Network. In: The First International Workshop on Wireless Networking for Intelligent Transportation Systems.

(2008) WIRELESS FAIR QUEUING ALGORITHM FOR WINDOW-BASED LINK LEVEL RETRANSMISSION. In: The sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08).

(2008) Bypass AODV: Improving Performance of Ad Hoc On-Demand Distance Vector (AODV) Routing Protocol in Wireless Ad Hoc Networks. In: First International Conference on Ambient Media and Systems (Ambi-Sys 2008), Feb. 2008, Quebce, Canada.

(2005) Performance of Heterogeneous Traffic in Roaming Based Sharing Multi Operator 4G WCDMA. In: the 2nd International Symposium on Wireless Communication Systems 2005 (ISWCS'05), Siena, Italy.

(2006) On the Performance of Downlink Power-Based Scheduling for Slotted CDMA Networks. In: 64th IEEE-VTC Fall 2006, Montreal, Canada.

(2007) An Improved MAC Algorithm for Enhanced Performance for Saturation and Non-Saturation Conditions in IEEE 802.11 WLANs. In: The Twelfth IEEE Symposium on Computers and Communications (ISCC'07, July 1-4, 2007,, Aveiro, Portugal..

(2007) An Entropy-Based Throughput metric for Fairly Evaluating WSN Routing Protocols. In: 15th IEEE International Conference on Network Protocols, Beijing, China.

(2007) A Generalized Energy-Aware Data Centric Routing For Wireless Sensor Network. In: IEEE International Conference on Signal Processing and Communication (ICSPC07), Dubai, United Arab Emirates (UAE)..

(2006) A Study on Network Sharing and Radio Resource Management in 3G and Beyond Mobiles Wireless Networks Supporting Heterogeneous Traffic. In: The 2nd IEEE Conference Information and Communication Technologies, 2006. ICTTA '06.

(2006) Adaptive QoS-Based Scheduler for 4G CDMA Wireless Networks. In: the 2nd IEEE Information and Communication Technologies, 2006. ICTTA '06.

(2006) On Optimizing Backoff Procedure to Enhance Throughput and Fairness For Wireless LANs. In: The 2nd IEEE Information and Communication Technologies, 2006. ICTTA '06.

(1999) Adaptive admission policy for priority queue integrated CDMA networks. In: IEEE Wireless Communications and Networking Conference, 1999. WCNC, New Orleans, LA, USA.

(1998) A novel traffic control in ATM-based wireless networks. In: IEEE Canadian Conference on Electrical and Computer Engineering, 1998., Waterloo, Canada.

(2003) Adaptive admission/congestion control policy for hybrid TDMA/MC-CDMA integrated networks with guaranteed QoS. In: 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003, 14-17 Dec. 2003, Sharjah, UAE.

(2008) WIRELESS FAIR QUEUING ALGORITHM FOR WINDOW-BASED LINK LEVEL RETRANSMISSION. In: The sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08).

(2003) High Performance Elliptic Curve GF(2k) Crypto processor Architecture for Multimedia. In: IEEE International Conference on Multimedia & Expo, ICME 2003, July 6-9, 2003, Baltimore, Maryland, USA.

(2003) Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation. In: The 13th ACM Great Lakes Symposium on VLSI, April 28 - 29, 2003, Washington, D. C., USA.

(2007) Parallelizing GF(P) Elliptic Curve Cryptography Computations for Security and Speed. In: International Conference on Information Sciences, Signal Processing and their Applications (ISSPA), February 12-15, 2007, Sharjah, United Arab Emirates.

(2006) Scalable VLSI Design for Fast GF(p) Montgomery Inverse Computation. In: IEEE International Conference on Computer & Communication Engineering (ICCCE '06), 9-11 May 2006, Faculty of Engineering, International Islamic University Malaysia, Kuala Lumpur, Malaysia.

(2006) Pipelining GF(P) Elliptic Curve Cryptography Computation. In: The 4th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-06), March 8-11, 2006, American University of Sharjah (AUS), Sharjah, United Arab Emirates.

(2004) Super Pipelined Digit Serial Adders for Multimedia and e-Security. In: IEEE 1st International Computer Engineering Conference on New Technologies for the Information Society (ICENCO 2004), December 27-30, 2004, Faculty of Engineering, Cairo University, Cairo, EGYPT.

(2003) VLSI Core Architecture For GF(P) Elliptic Curve Crypto Processor. In: IEEE 10th International Conference on Electronics, Circuits and Systems (ICECS 2003), December 14-17, 2003, University of Sharjah, United Arab Emirates.

(2003) Fast Elliptic Curve Cryptographic Processor Architecture Based On Three Parallel GF(2k) Bit Level Pipelined Digit Serial Multipliers. In: IEEE 10th International Conference on Electronics, Circuits and Systems (ICECS 2003), December 14-17, 2003, University of Sharjah, United Arab Emirates.

(2003) Improving Cryptographic Architectures by Adopting Efficient Adders in their Modular Multiplication Hardware VLSI. In: The 9th Annual Gulf Internet Symposium, October 13-15, 2003, Khobar, Saudi Arabia.

(2003) Efficient Scalable Hardware Architecture for Montgomery Inverse Computation in GF(P). In: IEEE Workshop on Signal Processing Systems (SIPS’03), August 27-29, 2003, Seoul, Korea.

(2003) GF(2k) Elliptic Curve Cryptographic Processor Architecture Based on Bit Level Pipelined Digit Serial Multiplication. In: ACS/IEEE International Conference on Computer Systems and Applications (AICCSA'03), July 14-18, 2003, Tunisia.

(2002) Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation. In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI’02, April 25-26, 2002, Pittsburgh, Pennsylvania, USA.

(2002) Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2n). In: Workshop on Cryptographic Hardware and Embedded Systems CHES’2002, August 13-15, 2002, San Francisco Bay (Redwood City), USA.

(2003) High Radix Parallel Architecture For GF(p) Elliptic Curve Processor. In: IEEE Conference on Acoustics, Speech, and Signal Processing, ICASSP 2003, April 6-10, 2003, Hong Kong.

(2007) A Novel Arabic Text Steganography Method Using Letter Points and Extensions. In: WASET International Conference on Computer, Information and Systems Science and Engineering (ICCISSE), May 25-27, 2007, Vienna, Austria.

(2008) Efficient Adders to Speedup Modular Multiplication for Cryptography. In: WoSPA 2008 - International Workshop on Signal Processing and its Applications, 18 – 20 March 2008, University of Sharjah, Sharjah, U.A.E..

(1999) An Expandable Montgomery Modular Multiplication Processor. In: ICM '99: The Eleventh International Conference on Microelectronics, 22-24 Nov. 1999, Kuwait.

(2007) Approximation Techniques For Analytical Characterization Of Downlink Traffic Power For Multi-Service CDMA Networks. In: 15th IEEE International Conference on Networks (ICON2007), 19-21 November, 2007, Adelaide, South Australia.

(2007) Performance Analysis of Adaptive Rate Scheduling Scheme for 3G WCDMA Wireless Networks with Multi-Operators. In: IEEE International Conference on Communications 2007 - ICC-2007, 24-28 June 2007, Glasgow, Scotland.

(2007) Downlink Traffic Power Characterization for Multi- Rate Wireless CDMA Data Networks. In: 2007 IEEE 66th Vehicular Technology Conference, 30 September - 3 October 2007, Baltimore, MD, USA.

Static Weighted Load-balancing for XML-based Network Management using JPVM. In: The 8th IFIP/IEEE International Conference on Management of Multimedia Networks and Services (MMNS 2005), October 24-26, 2005, Barcelona, Spain.

Optimising OSPF Routing for Link Failure Scenarios. In: Optimising OSPF Routing for Link Failure. (Unpublished)

An Adaptive Load-balancing Approach to XML-based Network Management using JPVM. In: An Adaptive Load-balancing Approach to XML-based Network Management using JPVM, November 16-18, 2005, Kuala Lumpur, Malaysia.

(2007) Effective Parallelization of Stochastic Evolution. In: ISDA'07 Conference. (Unpublished)

(2006) Parallel Stochastic Evolution Algorithms for Constrained Multiobjective Optimization. In: SNPD'07. (Unpublished)

Trends in Internet Usage & its Social Effects in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

Storage Media. In: Department of Computer Engineering, KFUPM.

Storage Media[Compatibility Mode]. In: Department of Computer Engineering, KFUPM.

STRATEGIC RESEARCH PROJECTS BRIEF. In: Department of Computer Engineering, KFUPM.

Structured Backbone Design of CNs. In: Department of Computer Engineering, KFUPM.

“Summary Report” Structure of National IT Plan for Saudi Arabia. In: Department of Computer Engineering, KFUPM.

Synchronous /Asynchronous Transmission. In: Department of Computer Engineering, KFUPM.

Tabu Search Based Circuit Optimization. In: Department of Computer Engineering, KFUPM.

(2005) Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm. In: International Symposium on Circuits and Systems, (ISCAS 05), Kobe, Japan.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: International Symposium on Circuits and Systems, (ISCAS 06), Kos, Greece.

Introduction to TCP/IP. In: Departement of Computer Engineering, KFUPM, Dhahran, Saudi Arabia.

TCP/IP. In: Department of Computer Engineering, KFUPM.

Strategy Planning for Higher Education Project Horizon. In: King Fahd University of Petroleum & Minerals.

The Aafaq Web. In: Department of Computer Engineering, KFUPM.

(2001) Iterative Heuristics for Timing & low power VLSI standard cell placement. In: Unknown. (Unpublished)

Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. In: KFUPM Project Number COE/ITERATE/221, KFUPM.

The COE Department. In: Computer Engineering Department, KFUPM.

Transmission Media. In: Department of Computer Engineering, KFUPM.

Use and Effect of Internet in Saudi Arabia. In: Department of Computer Engineering, KFUPM.

Modern Digital System Design Using VHDL: A Practical Introduction. In: Department of Computer Engineering, KFUPM.

WWW & E-Commerce. In: Department of Computer Engineering, KFUPM.

Web Database Connectivity. In: Computer Engineering Department, KFUPM.

Windows NT Installation. In: Department of Computer Engineering, King Fahd University of Petroleum and Minerals.

Active Directory. In: Departement of Computer Engineering, KFUPM, Dhahran, Saudi Arabia.

(2006) Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement. In: International Parallel and Distributed Processing Symposium, April, 2006, Rhodes Island, Greece.

(2005) Comparative Evaluation of Parallelization Strategies for Evolutionary and Stochastic Heuristics. In: Genetic and Evolutionary Computation Conference (GECCO-2005),, 25-29 June, 2005, Washington D.C. , USA.

(2005) Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning. In: Unknown.

FUZZIFIED SIMULATED EVOLUTION ALGORITHM FOR MULTI-OBJECTIVE OPTIMIZATION OF COMBINATIONAL LOGIC CIRCUITS. In: Computer Engineering Department, KFUPM.

Fast Fuzzy Force-Directed/Simulated Evolution Metaheuristic for Multiobjective VLSI Cell Placement. In: Department of Computer Engineering, KFUPM.

(2001) Modern Iterative Algorithms and thier Applications in Computer Engineering. In: Book.

EFFICIENT COMBINATIONAL CIRCUITS DESIGN THROUGH FUZZIFIED ANT COLONY OPTIMIZATION ALGORITHM. In: Computer Engineering Department, KFUPM.

Computer Engineering Department Research Profile. In: Computer Engineering Department, KFUPM.

Information Technology Center (ITC) Services and Projects. In: Supporting excellence via technology, KFUPM.

CCSE PAST & PRESENT STANDING. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

(2003) Iterative Computer Algorithms with Applications in Engineering-Chapter 2: Partitioning. In: College of Computer Sciences & Engineering, King Fahd University of Petroleum & Minerals.

Chapter 1: Introduction to VLSI Physical Design. In: King Fahd University of Petroleum & Minerals.

Automating Your Schedule. In: Special Mini Talk/Demo for 993 Summer, Dhahran, Saudi Arabia.

An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation. In: An Iterative Heuristic for State Justification in, Dhahran, Saudi Arabia.

Area-Time Optimal Adder with Relative Placement Generator. In: Area-Time Optimal Adder with Relative Placement Generator.

Iterative Computer Algorithms: and their applications in engineering. In: Special Talk for Motorola CAD Group,.

(2007) Arabic Diacritics Based Steganography. In: IEEE International Conference on Signal Processing and Communications (ICSPC 2007), 24-27 November 2007, Dubai, UAE.

(2000) A Parallel Tabu Search Algorithm for VLSI Standard-Cell Placement. In: IEEE International Symposium on Circuits and Systems'', Geneva.

(2000) Fuzzy Simulated Evolution Algorithm for Topology Design on Campus Networks. In: IEEE Congress on Evolutionary Computation, San Diego, USA.

(1999) Fuzzy Simulated Evolution Algorithm for Multiobjective Optimization of VLSI Placement. In: IEEE Congress on Evolutionary Computation, Washington DC.

(1995) Timing Influenced General-Cell Genetic Floorplanner. In: Asia and South-Pacific Design Automation Conference, ASP-DAC'95, Japan.

(1995) Timing Influenced Force Directed Floorplanning. In: European Design Automation Conference with Euro-VHDL, Euro-DAC'95, Brighton.

(1995) A Novel Technique for Fast Multiplication. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1995) Timing Driven Genetic Algorithm for Placement. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1995) Performance Driven Standard-cell Placement Using the Genetic Algorithm. In: Fifth Great Lakes Symposium on VLSI, GLSVLSI'95, Buffalo, USA.

(1995) Loop based scheduling for high level synthesis. In: IEEE Phoenix Conference on Computers and Communications, IPCCC.

(1994) Design of a Cell Library for Formal High-level Synthesis. In: IEEE Melecon'94.

(1994) ASIC Design with AHPL. In: IEEE Melecon'94.

(1992) High Level Synthesis of Controllers for Communication Protocols. In: Second Great Lakes Symposium on VLSI, GLSVLSI'92, Kalamazoo.

(1992) VLSI Implementation of Controllers for Communication Protocols from their Petri Net Models. In: IEEE International Symposium on Circuits and Systems, California.

(1991) A State Machine Synthesizer with Weinberger Arrays. In: The IEEE Pacific RIM Conference, Victoria, Canada.

(1989) A Systolic Algorithm for VLSI Design of a Rate Viterbi Decoder. In: IEEE Melecon'89, Portugal.

(1994) GSA: Scheduling and Allocation using Genetic Algorithm. In: European Design Automation Conference with Euro-VHDL, Euro-DAC'94, Grenoble.

(1998) Tabu Search Based Circuit Optimization. In: Great Lakes Symposium on VLSI, GLSVLSI'98, SW Louisiana.

(1998) Performance and Interface Buffer Size Driven Behavioral Partitioning for Embedded Systems. In: 9th International Workshop on Rapid Systems Prototyping, IEEE Computer Society Sponsored, Leuven, Belgium.

(1998) Buffer Size Driven Partitioning for HW/SW Co-Design. In: IEEE International Conference on Computer Design, ICCD'98, Austin, USA.

(1999) A High-Performance Hardware-EÆcient Memory Allocation Technique and Design. In: IEEE International Conference on Computer Design, ICCD'99, Austin, USA.

(2001) Task Matching and Scheduling in Heterogeneous Systems Using Simulated Evolution. In: 10th Heterogeneous Computing Workshop in conjunction with IPDPS 2001, San Francisco.

(2001) Fuzzy Evolutionary Hybrid Metaheuristic for Network Topology Design. In: International Conference on Evolutionary Multi-Criterion Optimization, EMO'01, ETH Zurich, Switzerland (A Springer Publication).

(2001) Adaptive Bias Simulated Evolution Algorithm for Placement. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) A Fast Constructive Algorithm For Fixed Channel Assignment Problem. In: IEEE 2001 International Symposium on Circuits and Systems, Sydney, Australia.

(2001) Fuzzy Evolutionary Algorithm for VLSI Placement, (Spector, L., E. Goodman, A. Wu, W. B. Langdon, H.-M. Voigt, M. Gen, S. Sen, M. Dorigo, S. Pezeshk, M. Garzon, and E. Burke, editors). In: Proceedings of the Genetic and Evolutionary Computation Conference, GECCO-2001, San Francisco, CA.

(2001) An Evolutionary Algorithm for Network Topology Design. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzy Simulated Evolution for Power and Performance Optimization of VLSI Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Iterative Heuristics for Multiobjective VLSI Cell Placement. In: International Joint INNS-IEEE Conference on Neural Networks, Washington D.C, USA.

(2001) Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. In: IEEE International Conference on Computer Design, ICCD'2001, Austin.

(2002) HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) PERFORMANCE AND LOW POWER DRIVEN VLSI STANDARD CELL PLACEMENT USING TABU SEARCH. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2002) FUZZY AGGREGATING FUNCTIONS FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE International Conference on Fuzzy Systems', Honolulu, Hawaii, USA.

(2002) FUZZY BIASLESS SIMULATED EVOLUTION FOR MULTIOBJECTIVE VLSI PLACEMENT. In: IEEE Congress on Evolutionary Computation'', Honolulu, Hawaii, USA.

(2003) Parallel Tabu Search in a Heterogeneous Environment. In: Proceedings of 17th International Parallel & Distributed Processing Symposium.

(2003) GENERAL ITERATIVE HEURISTICS FOR VLSI MULTIOBJECTIVE PARTITIONING. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Simulated Evolution Algorithm For Multiobjective VLSI Netlist Bi-Partitioning. In: IEEE International Symposium on Circuits and Systems', Bangkok, Thailand.

(2003) AREA-TIME OPTIMAL ADDER WITH RELATIVE PLACEMENT GENERATOR. In: IEEE International Symposium on Circuits and Systems'', Bangkok, Thailand.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part I: Enumerative Techniques. In: IEEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) Reliability and Fault Tolerance based Topological Optimization of Computer Networks - Part II: Iterative Techniques. In: EEE Pacific Rim Conference, Victoria, BC, Canada.

(2003) ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING. In: IEEE International Symposium on Circuits and Systems, Sharjah, UAE.

(2003) Digital Circuit Design Through Simulated Evolution (SimE). In: IEEE Congress on Evolutionary Computation (CEC),, Canberra, Australia.

(2003) A Modified Ant Colony Algorithm for Evolutionary Design of Digital Circuits. In: IEEE Congress on Evolutionary Computation, Canberra, Australia.

(2004) FAST FORCE-DIRECTED/SIMULATED EVOLUTION HYBRID FOR MULTIOBJECTIVE VLSI CELL PLACEMENT. In: IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada.

(2004) Fuzzified Ant Colony Optimization Algorithm for Efficient Combinational Circuits Synthesis. In: IEEE Congress on Evolutionary Computation (CEC),, Portland Oregon, USA.

(2004) Enhanced Simulated Evolution Algorithm For Digital Circuit Design Yielding Faster Execution in a Larger Solution Space. In: IEEE Congress on Evolutionary Computation (CEC),, Portland, Oregon, USA.

(2005) Multiobjective VLSI Cell Placement using Distributed Genetic Algorithm. In: Genetic and Evolutionary Computation Conference (GECCO-2005), Washington D.C. , USA.

(2005) Efficient Static Compaction Techniques for Sequential Circuits based on Reverse Order Restoration Based and Test Relaxation. In: Proceedings of the 14th Asian Test Symposium (ATS ’05), Kolkata, India.

(2006) An Enhanced Estimator to Multi-objective OSPF WeightSetting Problem. In: Proceedings of 2006 IEEE/IFIP Network Operations & Management Symposium (NOMS 2006),, Vancouver, Canada.

(2006) Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement. In: Proceedings of 2006 International Symposium in Circuits and Systems, pages 4615-4618, (ISCAS 2006), Island of Kos, Greece.

(2006) Finite State Machine State Assignment for Area and Power Minimization. In: Proceedings of 2006 International Symposium in Circuits and Systems, (ISCAS 2006), Island of Kos, Greece.

(2006) A Heuristics Based Approach for Cellular Mobile Network Planning. In: The International Wireless Communications and Mobile Computing Conference (IWCMC06), Vancouver, Canada.

(2007) Message Concealment Techniques using Image based Steganography. In: The 4th IEEE GCC Conference, 11-14 Nov. 2007, Gulf International Convention Centre, Bahrain.

Monograph

(2000) A Modulo Multiplication Hardware Design. Project Report. Professor C. Koc, Oregon State University, ECE 575 Project Report.

(2005) Speeding Up a Scalable Modular Inversion Hardware Architecture. Project Report. KFUPM, Bio-Inspired Intelligent System (BIIS) research group.

(2003) High Speed Low Power GF(2k) Elliptic Curve Cryptography Processor Architecture. Technical Report. IEEE 10th Annual Technical Exchange Meeting, KFUPM, Dhahran 31261, Saudi Arabia.

Other

(2004) Parallelization of Stochastic Evolution for Cell Placement. KFUPM. (Unpublished)

Parallelization of Stochastic Evolution for Cell Placement. KFUPM. (Unpublished)