Article

(1993) Design and Analysis of a High Speed Sense Amplifier for Single Transistor Non-Volatile Memory Cells. IEE Proceedings G on Circuits, Devices and Systems, 140 (2). pp. 117-122.

(1992) Design, Selection and Implementation of Flash Erase EEPROM Memory Cell Structures. IEE Proceedings G on Circuits, Devices and Systems, 139 (3). pp. 370-376.

(1993) A Speed-Optimized Array Architecture for Flash EEPROMS. IEE Proceedings G on Circuits, Devices and Systems, 140 (3). pp. 177-181.

(1996) A Generic DFT Approach for Pattern Sensitive Faults in Word-Oriented Memories. IEE Proceedings E on Computers and Digital Techniques, 143 (3). pp. 199-202.

(2006) A High-Speed Self-Timed Carry-Skip Adder. IEE Proceedings - Circuits, Devices and Systems, 153 (6). pp. 574-582.

(2007) Area-Efficient High-Speed Carry Chain. IET Electronics Letters, 43 (23). pp. 1258-1260.

(1997) New Fault Models and Efficient BIST Algorithm for Dual Port Memories. IEEE Transations on CAD of Integrated Circuits and Systems, 16 (9). pp. 987-1000.

(2006) Hardware Implementations of GF(2^m) Arithmetic using Normal Basis. Journal of Applied Sciences, 6 (6). pp. 1362-1372.

Conference or Workshop Item

(2007) Utilizing Extension Character ‘Kashida’ With Pointed Letters For Arabic Text Digital Watermarking. In: International Conference on Security and Cryptography - SECRYPT, July 28 - 31, 2007, Barcelona, Spain.

(1999) An Expandable Montgomery Modular Multiplication Processor. In: ICM '99: The Eleventh International Conference on Microelectronics, 22-24 Nov. 1999, Kuwait.