Area-Efficient High-Speed Carry Chain

(2007) Area-Efficient High-Speed Carry Chain. IET Electronics Letters, 43 (23). pp. 1258-1260.

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An improved carry chain circuit with carry-skip capability is described. The carry-skip logic allows an arbitrarily long carry chain without the need for intermediate buffers for signal restoration, leading to an implementation that is both fast and area-efficient. The chain can flexibly accommodate technology-imposed maximum depth of NMOS transistor pull-down stack.

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Obaid-Ur-Rehman Khattak
Date Deposited: 28 Apr 2008 12:24
Last Modified: 01 Nov 2019 13:26