A High-Speed Self-Timed Carry-Skip Adder

(2006) A High-Speed Self-Timed Carry-Skip Adder. IEE Proceedings - Circuits, Devices and Systems, 153 (6). pp. 574-582.

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An efficient self-timed carry-skip adder with low area overhead and fast operation is proposed. The adder combines delay-insensitive and bounded delay completion signal detection techniques to define a novel, reliable, area-efficient and high-speed completion-detection circuit. The circuit employs double-rail encoded carry signals together with process-tracking delay circuit elements to efficiently produce a final completion signal of tight acknowledge slack time under different operating conditions. In addition the proposed adder employs carry-skip speed-up circuitry resulting in a novel self-timed carry-skip adder that is quite efficient in terms of both speed and area

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Obaid-Ur-Rehman Khattak
Date Deposited: 28 Apr 2008 12:24
Last Modified: 01 Nov 2019 13:26
URI: https://eprints.kfupm.edu.sa/id/eprint/1239