Design and Analysis of a High Speed Sense Amplifier for Single Transistor Non-Volatile Memory Cells

(1993) Design and Analysis of a High Speed Sense Amplifier for Single Transistor Non-Volatile Memory Cells. IEE Proceedings G on Circuits, Devices and Systems, 140 (2). pp. 117-122.

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Abstract

Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32k EPROM memory chip using 1.5 μm N-well CMOS process

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Obaid-Ur-Rehman Khattak
Date Deposited: 28 Apr 2008 12:33
Last Modified: 01 Nov 2019 13:26
URI: https://eprints.kfupm.edu.sa/id/eprint/1233