Speed optimised array architecture for flash EEPROMs

(1993) Speed optimised array architecture for flash EEPROMs. Circuits, Devices and Systems, IEE Proceedings G, 140.

[img]
Preview
PDF
14216_1.pdf

Download (18kB) | Preview
[img] Microsoft Word
14216_2.doc

Download (26kB)

Abstract

The author describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells

Item Type: Article
Subjects: Petroleum
Divisions: College Of Engineering Sciences > Chemical Engineering Dept
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 16:27
Last Modified: 01 Nov 2019 17:04
URI: http://eprints.kfupm.edu.sa/id/eprint/14216