Modeling and Analysis of Interrupt Disable-Enable Scheme

Modeling and Analysis of Interrupt Disable-Enable Scheme. Proceedings of the IEEE 21st International Conference on Advanced Information Networking and Applications (AINA-07), Niagara Falls, Canada. pp. 1000-1005.

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Abstract

System performance of Gigabit network hosts can severely be degraded due to interrupt overhead caused by heavy incoming traffic. One of the most popular solutions to mitigate such overhead is interrupt disabling and then enabling. In this solution, interrupt overhead is significantly reduced by disabling interrupts and only re-enabling them after processing all queued packets. In this paper we investigate analytically the performance of the scheme of interrupt disabling and enabling and compare it with normal interruption and interrupt coalescing. The system performance is analyzed and compared in terms of throughput, latency, and CPU availability for user applications.

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Information and Computer Science
Depositing User: KHALED HAMED SALAH
Date Deposited: 26 Mar 2008 11:37
Last Modified: 01 Nov 2019 13:25
URI: https://eprints.kfupm.edu.sa/id/eprint/742