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    STATE MACHINE SYNTHESIS WITH WEINBERGER ARRAYS

    STATE MACHINE SYNTHESIS WITH WEINBERGER ARRAYS. INTERNATIONAL JOURNAL OF ELECTRONICS 71 (1): 1-12 JUL 1991.

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    Abstract

    Abstract The development of a digital circuit synthesis program is described. The program accepts the transition table of a state machine and returns equations for an implementation that assumes a sum-of-product next-state and output functions. From the equations for the next-state and output functions, nMOS VLSI layout for a Weinberger array is generated. D flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts can be generated automatically from state table descriptions. Keywords: design

    Item Type: Article
    Subjects: Computer
    Department: College of Computing and Mathematics > Computer Engineering
    Depositing User: AbdulRahman
    Date Deposited: 11 Mar 2008 07:10
    Last Modified: 01 Nov 2019 13:23
    URI: http://eprints.kfupm.edu.sa/id/eprint/299