Efficient Scalable VLSI Architecture for Montgomery Inversion in GF(p)

(2004) Efficient Scalable VLSI Architecture for Montgomery Inversion in GF(p). Integration, the VLSI Journal, 37 (2). pp. 103-120. ISSN 0167-9260

[img] HTML (Abstract)

Download (9kB)
PDF (Paper)

Download (209kB) | Preview


The multiplicative inversion operation is a fundamental computation in several cryptographic applications. In this work, we propose a scalable VLSI hardware to compute the Montgomery modular inverse in GF(p). We suggest a new correction phase for a previously proposed almost Montgomery inverse algorithm to calculate the inversion in hardware. We also propose an efficient hardware algorithm to compute the inverse by multi-bit shifting method. The intended VLSI hardware is scalable, which means that a fixed-area module can handle operands of any size. The word-size, which the module operates, can be selected based on the area and performance requirements. The upper limit on the operand precision is dictated only by the available memory to store the operands and internal results. The scalable module is in principle capable of performing infinite-precision Montgomery inverse computation of an integer, modulo a prime number. This scalable hardware is compared with a previously proposed fixed (fully parallel) design showing very attractive results.

Item Type: Article
Subjects: Math
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: ADNAN ABDU GUTUB (gutub
Date Deposited: 01 Mar 2008 13:38
Last Modified: 01 Nov 2019 13:22
URI: http://eprints.kfupm.edu.sa/id/eprint/176