(2007) PARALLEL COMPUTING PLATFORM FOR EVALUATING LDPC CODES PERFORMANCE. IEEE International Conference on Signal Processing and Communications. pp. 157-160.
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Abstract
This paper presents a novel approach for the design and implementation of a simulation platform for evaluating LDPC codes performance. The existing LDPC code simulation tools consume very long time in evaluating the performance of a specific code design. This is due to the intensive number of required computations. This problem is overcome by developing a parallel protocol to distribute the computations among processing nodes in a TCP/IP network. As indicated by experimental results, the proposed simulation platform is scalable with the number of processing nodes. Another practical advantage of the proposed system is that it does not need dedicated processors to run it; rather, it can utilize idle times of processing nodes in a network and work transparent to a node user. Furthermore, network daemons are used to utilize network nodes even if they are in the log-off state.
| Item Type: | Article |
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| Subjects: | Computer Electrical |
| Department: | College of Computing and Mathematics > Computer Engineering |
| Depositing User: | AIMAN HELMI EL-MALEH |
| Date Deposited: | 01 Mar 2008 08:29 |
| Last Modified: | 01 Nov 2019 13:22 |
| URI: | http://eprints.kfupm.edu.sa/id/eprint/166 |