(2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5.

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Abstract

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.

Item Type:	Article
Subjects:	Computer
Department:	College of Computing and Mathematics > Computer Engineering
Depositing User:	Mr. Admin Admin
Date Deposited:	24 Jun 2008 13:49
Last Modified:	01 Nov 2019 14:07
URI:	http://eprints.kfupm.edu.sa/id/eprint/14799