A new static differential CMOS logic with superior low power performance

(2003) A new static differential CMOS logic with superior low power performance. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 2.

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Abstract

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Its performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. SPICE simulations using a 0.18 /spl mu/m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 13:49
Last Modified: 01 Nov 2019 14:07
URI: https://eprints.kfupm.edu.sa/id/eprint/14779