Efficient O(n) BIST algorithms for DDNPS faults in dual portmemories. Test Conference, 1994. Proceedings., International, 1.

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Abstract

The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (DDNPSF)

Item Type:	Article
Subjects:	Computer
Department:	College of Chemicals and Materials > Chemical Engineering
Depositing User:	Mr. Admin Admin
Date Deposited:	24 Jun 2008 13:24
Last Modified:	01 Nov 2019 14:04
URI:	http://eprints.kfupm.edu.sa/id/eprint/14149