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    Double-rail encoded self-timed adder with matched delays

    (2003) Double-rail encoded self-timed adder with matched delays. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3.

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    Abstract

    An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.

    Item Type: Article
    Subjects: Computer
    Department: College of Chemicals and Materials > Chemical Engineering
    Depositing User: Mr. Admin Admin
    Date Deposited: 24 Jun 2008 13:24
    Last Modified: 01 Nov 2019 14:04
    URI: http://eprints.kfupm.edu.sa/id/eprint/14143