(1998) Buffer Size Driven Partitioning for HW/SW Co-Design. In: IEEE International Conference on Computer Design, ICCD'98, Austin, USA.

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Abstract

Abstract Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Results are compared with those produced by simulated annealing.

Item Type:	Conference or Workshop Item (Other)
Subjects:	Computer
Department:	College of Computing and Mathematics > Computer Engineering
Depositing User:	AbdulRahman
Date Deposited:	26 Feb 2008 05:13
Last Modified:	01 Nov 2019 13:22
URI:	http://eprints.kfupm.edu.sa/id/eprint/119