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AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS

El-Maleh, Aiman and Al-Suwaiyan, Ali AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002.

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Abstract

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude.



Item Type:Article
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Information and Computer Science Dept
Creators:El-Maleh, Aiman and Al-Suwaiyan, Ali
Email:aimane@ccse.kfupm.edu.sa, UNSPECIFIED
ID Code:1644
Deposited By:INVALID USER
Deposited On:02 Jun 2008 14:12
Last Modified:12 Apr 2011 13:11

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