KFUPM ePrints

An efficient test relaxation technique for combinational & full-scan sequential circuits

El-Maleh, A. and Al-Suwaiyan, A. (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, 1.

[img]
Preview
PDF
18Kb
[img]Microsoft Word
26Kb

Abstract

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.



Item Type:Article
Date:2002
Date Type:Publication
Subjects:Computer
Divisions:College Of Sciences > Chemistry Dept
Creators:El-Maleh, A. and Al-Suwaiyan, A.
ID Code:14181
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:25
Last Modified:12 Apr 2011 13:14

Repository Staff Only: item control page