Sait, Sadiq M. and Farooqui, A.A. and Beckhoff, G.F. (1995) A novel technique for fast multiplication. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.
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Abstract
In this paper we present the design of a new high speed multiplication unit. The design is based on non-overlapped scanning of 3-bit fields of the multiplier. In this algorithm the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and finally the sum and carry vectors are added using a carry-look-ahead adder. In case of 2's complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithms is modeled in a hardware description language and its VLSI chip implemented. The performance of the new design is compared with other recent ones proposed in literature
| Item Type: | Article |
|---|---|
| Date: | March 1995 |
| Date Type: | Publication |
| Subjects: | Computer |
| Divisions: | College Of Computer Sciences and Engineering > Computer Engineering Dept |
| Creators: | Sait, Sadiq M. and Farooqui, A.A. and Beckhoff, G.F. |
| Email: | sadiq@kfupm.edu.sa, UNSPECIFIED, UNSPECIFIED |
| ID Code: | 14170 |
| Deposited By: | KFUPM ePrints Admin |
| Deposited On: | 24 Jun 2008 16:25 |
| Last Modified: | 12 Apr 2011 13:15 |
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