(1995) A novel technique for fast multiplication. Computers and Communications, 1995. Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix conference, 1.

Preview	PDF 14170_1.pdf Download (18kB) | Preview
	Microsoft Word 14170_2.doc Download (26kB)

Abstract

In this paper we present the design of a new high speed multiplication unit. The design is based on non-overlapped scanning of 3-bit fields of the multiplier. In this algorithm the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and finally the sum and carry vectors are added using a carry-look-ahead adder. In case of 2's complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithms is modeled in a hardware description language and its VLSI chip implemented. The performance of the new design is compared with other recent ones proposed in literature

Item Type:	Article
Subjects:	Computer
Department:	College of Computing and Mathematics > Computer Engineering
Depositing User:	Mr. Admin Admin
Date Deposited:	24 Jun 2008 13:25
Last Modified:	01 Nov 2019 14:04
URI:	http://eprints.kfupm.edu.sa/id/eprint/14170