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Bit-level pipelined digit serial GF(2m) multiplier

Ibrahim, M.K. and Almulhem, A. (2001) Bit-level pipelined digit serial GF(2m) multiplier. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 4.

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Abstract

A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier



Item Type:Article
Date:May 2001
Date Type:Publication
Subjects:Computer
Divisions:College Of Computer Sciences and Engineering > Computer Engineering Dept
Creators:Ibrahim, M.K. and Almulhem, A.
ID Code:14133
Deposited By:KFUPM ePrints Admin
Deposited On:24 Jun 2008 16:23
Last Modified:12 Apr 2011 13:14

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