Interconnect-Efficient LDPC Code Design. In: Int’l Conf. on Microelectronics, Dec. 2006.

Full text not available from this repository.

Abstract

In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length, thus constraining the wire capacitance which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower the interconnect routing congestion, and hence reduce the chip area and maximize chip utilization.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	Electrical
Department:	College of Engineering and Physics > Electrical Engineering
Depositing User:	MOHAMMAD NURUZZAMAN
Date Deposited:	02 Jun 2008 08:46
Last Modified:	01 Nov 2019 13:25
URI:	http://eprints.kfupm.edu.sa/id/eprint/999