Data-flow expression evaluator for VLSI implementation.

(1987) Data-flow expression evaluator for VLSI implementation. Masters thesis, King Fahd University of Petroleum and Minerals.

[img]
Preview
PDF
9911.pdf

Download (12MB) | Preview

Arabic Abstract

-

English Abstract

This work involves the design and development of a numeric expression evaluating computing systems which can be added as a special purpose slave processor to a host computer. The Data-Flow Expression Evaluator (DFEE) would increase the performance of the host computer in terms of computation speed-up. The expression evaluation system is based on data-flow computing architecture. The architecture is further developed into a highly parallel circular pipelined computing architecture. This architecture is mapped into a Very Large Scale Integrated Circuit (VLSI) design which would be suitable for single chip VLSI implementation.

Item Type: Thesis (Masters)
Subjects: Electrical
Divisions: College Of Engineering Sciences > Electrical Engineering Dept
Committee Advisor: Beckhoff, Gerhard F.
Committee Members: Zafar, Z. and Rahman, M. A. A.
Depositing User: Mr. Admin Admin
Date Deposited: 22 Jun 2008 16:52
Last Modified: 01 Nov 2019 16:52
URI: http://eprints.kfupm.edu.sa/id/eprint/9911