A fault independent test generation method for combinational logic circuits

(1992) A fault independent test generation method for combinational logic circuits. Masters thesis, King Fahd University of Petroleum and Minerals.

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Arabic Abstract

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English Abstract

In order to improve the performance of fault independent test generation algorithms for VLSI combinational logic circuits, two new strategies are proposed: Critical Lines Maximization strategy (CLM) and Critical Primary inputs Flipping strategy (CPF). CLM is used to maximize the number of detected faults while generating a test pattern. CPF is used to derive new test pattern(s) from a generated test pattern with little additional effort. In this thesis, a new backtrace procedure, called CLM-Multiple-Backtrace, based on the CLM strategy as well as multiple backtrace procedure of FAN is introduced. A new fault independent test generation algorithm, called MAX, based on these new strategies as well as many other efficient strategies and procedures of the existing test generation algorithms is introduced and illustrated with examples. Experimental results show that MAX is more efficient than the fault independent test generation algorithms given in the literature.

Item Type: Thesis (Masters)
Subjects: Computer
Department: College Of Computer Sciences and Engineering > Information and Computer Science Dept
Committee Advisor: Arafeh, Bassel R.
Committee Members: Shafique, Muhammed and Osman, Mohamed Y. and Najjar, Mamdouh M.
Depositing User: Mr. Admin Admin
Date Deposited: 22 Jun 2008 13:50
Last Modified: 01 Nov 2019 13:51
URI: https://eprints.kfupm.edu.sa/id/eprint/9846