Efficient Adders to Speedup Modular Multiplication for Cryptography

(2008) Efficient Adders to Speedup Modular Multiplication for Cryptography. In: WoSPA 2008 - International Workshop on Signal Processing and its Applications, 18 – 20 March 2008, University of Sharjah, Sharjah, U.A.E..

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Abstract

Modular multiplication is an essential operation in many cryptography arithmetic operations. This work serves the modular multiplication algorithms focusing on improving their underlying binary adders. Different known adders have been considered and studied. The carry-save adder, carry-lookahead adder and carry-skip adder showed interesting features and trade-offs. The adders VHDL implementations gave some more beneficial details promising for improved crypto designs.

Item Type: Conference or Workshop Item (Poster)
Subjects: Math
Computer
Electrical
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: ADNAN ABDU GUTUB (gutub
Date Deposited: 29 Mar 2008 16:18
Last Modified: 01 Nov 2019 16:25
URI: http://eprints.kfupm.edu.sa/id/eprint/796