A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999.

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Abstract

In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and carry vectors are added using a carry-lookahead adder. In the case of 2 s complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithm is modelled in a hardware description language and its VLSI chip implemented. The performance of the new design is comparedwith that of other recent ones proposed in literature.

Item Type:	Article
Subjects:	Computer
Department:	College of Computing and Mathematics > Computer Engineering
Depositing User:	AbdulRahman
Date Deposited:	10 Mar 2008 05:46
Last Modified:	01 Nov 2019 13:23
URI:	http://eprints.kfupm.edu.sa/id/eprint/283