(1998) A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. 32nd Design Automation Congference. pp. 625-631.
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Abstract
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.
| Item Type: | Article |
|---|---|
| Subjects: | Computer |
| Department: | College of Computing and Mathematics > Computer Engineering |
| Depositing User: | AIMAN HELMI EL-MALEH |
| Date Deposited: | 03 Mar 2008 22:20 |
| Last Modified: | 01 Nov 2019 13:22 |
| URI: | http://eprints.kfupm.edu.sa/id/eprint/203 |