A Fault Independent Test Generation Method For Combinational Logic Circuits

(1992) A Fault Independent Test Generation Method For Combinational Logic Circuits. Masters thesis, KING FAHD UNIVERSITY OF PETROLEUM & MINERALS.

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Item Type: Thesis (Masters)
Subjects: Computer
Department: College Of Computer Sciences and Engineering > Information and Computer Science Dept
Depositing User: Users 4447 not found.
Date Deposited: 08 Jun 2008 09:16
Last Modified: 01 Nov 2019 13:29
URI: https://eprints.kfupm.edu.sa/id/eprint/1902