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    A Fault Independent Test Generation Method For Combinational Logic Circuits

    (1992) A Fault Independent Test Generation Method For Combinational Logic Circuits. Masters thesis, KING FAHD UNIVERSITY OF PETROLEUM & MINERALS.

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    Item Type: Thesis (Masters)
    Subjects: Computer
    Department: College of Computing and Mathematics > Information and Computer Science
    Depositing User: Users 4447 not found.
    Date Deposited: 08 Jun 2008 09:16
    Last Modified: 01 Nov 2019 13:29
    URI: http://eprints.kfupm.edu.sa/id/eprint/1902