(2006) Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 25 (11): 2556-2564 NOV 2006.
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Abstract
The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors’ technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques.
| Item Type: | Article |
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| Subjects: | Computer |
| Department: | College of Computing and Mathematics > Computer Engineering |
| Depositing User: | Mr. Admin Admin |
| Date Deposited: | 16 Sep 2007 08:24 |
| Last Modified: | 01 Nov 2019 13:21 |
| URI: | http://eprints.kfupm.edu.sa/id/eprint/17 |