Computer Engineering
Department, King Fahd University of Petroleum &
Minerals,
Email: gutub@kfupm.edu.sa
Abstract
In this paper, a fast hardware architecture
for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The
architecture is implemented for 160-bits, as its data size to handle. The
design adopts projective coordinates to eliminate most of the required GF(p)
inversion calculations replacing them with several multiplication operations. The
hardware is intended to be scalable, which allows the hardware to compute long
precision numbers in a repetitive way. The design involves four parallel
scalable multipliers to gain the best speed. This scalable design was
implemented in different versions depending on the area and speed. All scalable
implementations were compared with an available FPGA
design. The proposed scalable hardware showed interesting results in both area
and speed. It also showed some area-time flexibility to accommodate the variation
needed by different crypto applications.
Keywords: Modulo multipliers, Elliptic curve cryptography, Scalable hardware designs