Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits

(2003) Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits. ACM Transactions on Design Automation of Electronic Systems, 8 (4). pp. 430-459.

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Abstract

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this paper, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AIMAN HELMI EL-MALEH
Date Deposited: 01 Mar 2008 08:25
Last Modified: 01 Nov 2019 13:22
URI: https://eprints.kfupm.edu.sa/id/eprint/165