Interconnect-Efficient LDPC Code Design

(2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130.

[img]
Preview
PDF
Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf

Download (209kB) | Preview

Abstract

In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization.

Item Type: Article
Subjects: Computer
Electrical
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: AIMAN HELMI EL-MALEH
Date Deposited: 29 Feb 2008 23:36
Last Modified: 01 Nov 2019 16:22
URI: http://eprints.kfupm.edu.sa/id/eprint/162