An Improved Current Mirror Cell

An Improved Current Mirror Cell. In: the 4th ACS /IEEE international Conference on computer systems and applications, March 8-11,06, Dubai/Sharjah.

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A new configuration for the design of a current mirror is presented. The proposed configuration eliminates the DC matching error caused by the difference between drain-to-source voltages of both input and output transistors. The circuit can be used to enhance the accuracy of analog circuits for current levels from 0 to few hundreds microamperes The proposed configuration was verified by HSPICE simulator level 49 in 0.8m CMOS process technology. Simulation results show that DC matching error is substantially reduced compared to the cascade configuration

Item Type: Conference or Workshop Item (Paper)
Subjects: Electrical
Department: College of Engineering and Physics > Electrical Engineering
Date Deposited: 31 May 2008 12:27
Last Modified: 01 Nov 2019 13:27

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