High Speed Hardware Architecture to Compute GF(p) Montgomery Inversion with Scalability Features

(2007) High Speed Hardware Architecture to Compute GF(p) Montgomery Inversion with Scalability Features. IET (IEE) Proceedings Computers and Digital Techniques, 1 (4). pp. 389-396. ISSN 1751-861X

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Modular inversion is a fundamental process in several cryptographic systems. It can be computed in software or hardware, but hardware computation has been proven to be faster and more secure. This research focused on improving an old scalable inversion hardware architecture proposed in 2004 for finite field GF(p). The architecture comprises two parts, a computing unit and a memory unit. The memory unit holds all the data bits of computation whereas the computing unit performs all the arithmetic operations in word (digit) by word bases such that the design is scalable. The main objective of this paper is to show the cost and benefit of modifying the memory unit to include shifting, which was previously one of the tasks of the scalable computing unit. The study included remodeling the entire hardware architecture removing the shifter from the scalable computing part and embedding it in the non-scalable memory unit instead. This modification resulted in a speedup to the complete inversion process with an area increase due to the new memory shifting unit. Several design schemes have been compared giving the user the complete picture to choose from depending on the application need.

Item Type: Article
Subjects: Math
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: ADNAN ABDU GUTUB (gutub
Date Deposited: 29 Feb 2008 09:29
Last Modified: 01 Nov 2019 16:22
URI: http://eprints.kfupm.edu.sa/id/eprint/156