DFT for controlled-impedance I/O buffers

(2006) DFT for controlled-impedance I/O buffers. Design Automation Conference, 2006 43rd ACM/IEEE, 1.

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Abstract

This paper presents an architecture that enhances the testability of controlled-impedance buffers (CIBs). By testing CIBs digitally, the new architecture overcomes most of the problems with the traditional testing method. Most of these problems are test cost related. While reducing the test cost, the new architecture allows for higher test quality that even includes delay testing capabilities.

Item Type: Article
Subjects: Computer
Divisions: College Of Computer Sciences and Engineering > Computer Engineering Dept
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 16:33
Last Modified: 01 Nov 2019 17:05
URI: http://eprints.kfupm.edu.sa/id/eprint/14367