An Efficient Test Relaxation Technique for Synchronous Sequential Circuits

(2004) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits, 23 (6). pp. 933-940.

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Abstract

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Test-set relaxation can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify selfinitializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: AIMAN HELMI EL-MALEH
Date Deposited: 26 Feb 2008 23:10
Last Modified: 01 Nov 2019 13:22
URI: https://eprints.kfupm.edu.sa/id/eprint/143