Bit-level pipelined digit serial GF(2m) multiplier

(2001) Bit-level pipelined digit serial GF(2m) multiplier. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 4.

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Abstract

A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier

Item Type: Article
Subjects: Computer
Department: College of Computing and Mathematics > Computer Engineering
Depositing User: Mr. Admin Admin
Date Deposited: 24 Jun 2008 13:23
Last Modified: 01 Nov 2019 14:04
URI: https://eprints.kfupm.edu.sa/id/eprint/14133