An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits

(2002) An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. 20’th IEEE VLSI Test Symposium. pp. 53-59.

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Abstract

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.

Item Type: Article
Subjects: Computer
Divisions: College Of Computer Sciences and Engineering > Information and Computer Science Dept
Depositing User: AIMAN HELMI EL-MALEH
Date Deposited: 27 Feb 2008 00:53
Last Modified: 01 Nov 2019 16:22
URI: http://eprints.kfupm.edu.sa/id/eprint/141